# LPDDR4 Memory Controller for Nexus Devices

## Description

The Lattice Semiconductor LPDDR4 Memory Controller for Nexus Devices provides a turnkey solution consisting of a controller, DDR PHY, and associated clocking and training logic to interface with LPDDR4 SDRAM. The IP Core is implemented in System Verilog HDL using the Lattice Radiant software integrated with the Lattice Synthesis Engine (LSE) and Synplify Pro synthesis tools. The LPDDR4 Memory Controller simplifies the interfacing of CertusPro-NX and MachXO5T-NX devices with external LPDDR4 memory for user applications.

## Devices Supported

LFCPNX-100, LFCPNX-100AUTODIE, LFCPNX-50, LFMXO5-55T, LFMXO5-100T

## References

- User Guide

- LPDDR4 Memory Controller for Nexus Driver API Reference

- CertusPro-NX Memory Controller Driver User Guide

## Release Notes

2.4.0 | IP Release Notes
2.3.1 | Updated driver to add NOP delay when polling for training done. Disable dual rank option for 533MHz.
2.3.0 | Added driver support.
2.2.0 | Reduce AXI4 Read Latency. Added Dual Rank support. Added ODT programming support. Added Automatic Vref Training support. Fix write-read ordering issue when write queue is full. Added support for LFCPNX-100AUTODIE device.
2.1.0 | Added support for random AXI4 strobe. Added support for AXI4 data width less than DDR data width * 8. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
2.0.2 | Supported random AXI4 burst length from 1 to 64 beats. Supported any combination of burst length and burst size.
2.0.1 | Fixed Single access issues. Added Enable APB I/F option in the GUI. Enabled the No. of Outstanding Refresh Option and set the default value to 8. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
2.0.0 | Replace AHB-Lite and Native I/F with AXI4. Improve performance up to >80% DDR bus efficiency. Implemented Partial encryption to enable constraint propagation. Added 300MHz and 350MHz support. Validated all supported DDR clock frequencies on the board. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
1.3.0 | Added Vref training support for CA Vref, Controller's DQ Vref, and Memory DQ Vref. Improved Read performance for Native I/F. Added testbench for running simulation. Removed DDR3 support for this Memory Controller IP. Updated GUI options: ECC is fixed to Disabled, Internal RISC-V CPU is fixed to Enabled.
1.2.1 | Added limitation for DDR3. The DDR Interface Type GUI option has been fixed to LPDDR4.
1.2.0 | Updated for Radiant 3.1. Updated eval files to add the design for testing the IP on the board. Updated training logic to work on the board. Added Native I/F local data bus.
1.1.0 | Updated for Radiant 3.0. Added support for Micron WDQS Control Mode 2.
1.0.0 | Initial release.