Universal Asynchronous Receiver/Transmitter (UART) Transceiver IP Core performs serial-to-parallel conversion on data characters received from a peripheral UART device and parallel-to-serial conversion on data characters received from the Host located inside the FPGA through an APB Interface.
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| 1.4.0 | IP Release Notes |
| 1.3.1 | Updated assigned value for attributes used for enabling parity enable, odd parity, and sticky parity. |
| 1.3.0 | Updated to support all devices. |
| 1.2.0 | Added MachXO3L and MachXO3LF device support. |
| 1.1.1 | Added MachXO2 device support |
| 1.1.0 | Added LIFCL, LFD2NX and MachXO3D device support |
| 1.0.0 | Initial release. |