Universal Asynchronous Receiver/Transmitter (UART) Transceiver IP Core performs serial-to-parallel conversion on data characters received from a peripheral UART device and parallel-to-serial conversion on data characters received from the Host located inside the FPGA through an APB Interface.
LIFCL, LFD2NX, MachXO3D, MachXO2, MachXO3L, MachXO3LF
| 1.2.0 | Added MachXO3L and MachXO3LF device support. |
| 1.1.1 | Added MachXO2 device support |
| 1.1.0 | Added LIFCL, LFD2NX and MachXO3D device support |
| 1.0.0 | Initial release. |