The Lattice Semiconductor SubLVDS Image Sensor Receiver Submodule IP converts double data rate interface to pixel clock domain.The subLVDS interface is primarily used in image sensors. It has one clock pair and more than one data pairs. The number of data pairs varies, depending on bandwidth requirement.
Crosslink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant, Certus-N2
| 1.6.0 | IP Release Notes |
| 1.5.0 |
Added Certus-N2 support. |
| 1.4.0 |
Added APB implementation. Added AXI4-Stream implementation. Added bus_interface and memory_map.xml Modified metadata to enable APB and AXI4-Stream and insert APB and AXI4-Stream port signals. Updated constraint file. Added Avant-E/G/X device support. |
| 1.3.0 |
Added Propel support. Added Lattice Avant support. Added Lane Width 14. Added contraint file. Added LFMXO5 support. |
| 1.2.0 |
Added LFMXO5-25 support. Added Lane Widths 12 and 16. |
| 1.1.1 | Fixed clock constraint. |
| 1.1.0 | Added CertusPro-NX support. |
| 1.0.3 | Updated Testbench. |
| 1.0.2 | Minor Fixes. |
| 1.0.1 | Updated for SP1. |
| 1.0.0 | Initial release. |