SPI Master

Description

The SPI Master Controller IP provides a bridge between LMMI/AHB-Lite/APB interface and standard external SPI bus interface.

Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100

References

Revision History

1.1.0 Added CertusPro-NX support.
1.0.2 Desired SCLK Frequency maximum value is now 'System Clock Frequency'/2. Reduced APB/AHB-Lite read latency from 2 to 1.
1.0.1 Added Certus-NX support.
1.0.0 Preliminary release.