SPI Flash Controller

Description

The Serial Peripheral Interface (SPI) Flash Memory Controller IP Core provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device. The controller has two separate ports: Data Port Advanced High-performance Bus (AHB-Lite) interface and Control Port Advanced Peripheral Bus (APB) interface. Data Port can be used by the CPU to directly read from or write to any memory location within the SPI flash. Control Port can be used to define and set how SPI flash transactions are executed by the controller. The Control Port can also be used to perform commonly used flash operations for example, erase, page program, and read.

Devices Supported

CrossLink-NX, Certus-NX, CertusPro-NX, Certus-NX-RT, CertusPro-NX-RT, MachXO5, Lattice Avant

References

Release Notes

2.0.0
  • IP Release Notes
    		•
    1.9.0 Added AHB-L pipeline write access test sequence on testbench.
    1.8.1 Added HREADY input port on AHB-L bus interface.
    1.8.0 Updated IP constraints.
     Updated buffer write and read address logic.
     Updated supported flash commands.
     Updated IP driver.
    1.7.0 Added status registers.
     Added "Flash Memory Map Size" IP GUI attribute.
     Updated testbench. Added status register checks in between transactions.
    1.6.0 Updated controller output for user-defined command registers.
     Removed option to set the sector size on the GUI.
    1.5.0 Updated controller output for status read register.
     Updated generated IP constraints.
     Added clock polarity and phase attribute setting and register.
    1.4.0 Added UT24C, UT24CP and LAV-AT support.
     Added AHB-L support for page buffer program and read.
    1.3.1 Separated memory mapping for AHB-L and APB in Propel.
    1.3.0 Added Propel support.
     Separated AHB-L and APB clock.
     Added "Data Port AHB Data Byte Endianness" and "First Transmitted Bit" attributes.
     Set "Control Port APB Address Width" attribute value to 11 only.
     Added support for 32-bit SPI Flash addressing.
     Improved user command registers.
     Added register for SCLK Rate attribute.
    1.2.0 Added LFMXO5 support.
     Removed option to enable/disbale Control Port.
     Enabled the Control Port always.
    1.1.0 Added CertusPro-NX support.
    1.0.0 Initial release.