The Serial Peripheral Interface (SPI) flash controller provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.
The controller has two separate slave ports: Port S and Port C.
Port S can be used by the CPU to read from, or write to, any memory location within the SPI flash.
Port C provides a mechanism to configure the SPI flash and issue any command from the SPI Flash's command set.
LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100, LFMXO5-25
| 1.2.0 | Added LFMXO5 support AND removed option to enable/disbale Control Port. The Control Port is always enabled. |
| 1.1.0 | Added CertusPro-NX support. |
| 1.0.0 | Initial release. |