/* ================================================================== >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< ------------------------------------------------------------------ Copyright (c) 2006-2018 by Lattice Semiconductor Corporation ALL RIGHTS RESERVED ------------------------------------------------------------------ IMPORTANT: THIS FILE IS AUTO-GENERATED BY LATTICE RADIANT Software. Permission: Lattice grants permission to use this code pursuant to the terms of the Lattice Corporation Open Source License Agreement. Disclaimer: Lattice provides no warranty regarding the use or functionality of this code. It is the user's responsibility to verify the user Software design for consistency and functionality through the use of formal Software validation methods. ------------------------------------------------------------------ Lattice Semiconductor Corporation 111 SW Fifth Avenue, Suite 700 Portland, OR 97204 U.S.A Email: techsupport@latticesemi.com Web: http://www.latticesemi.com/Home/Support/SubmitSupportTicket.aspx ================================================================== */ #ifndef SPI_MASTER_H #define SPI_MASTER_H #include #include #define SPI_MASTER_DRV_VER "v1.4.1" #define SPI_CONTROLLER_DRV_VER "v1.4.1" #define SPI_SLAVE_0 0x01 #define SPI_SLAVE_1 0x02 #define SPI_SLAVE_2 0x04 #define SPI_SLAVE_3 0x08 #define SPI_SLAVE_4 0x10 #define SPI_SLAVE_5 0x20 #define SPI_SLAVE_6 0x40 #define SPI_SLAVE_7 0x80 #define SPI_FIFO_DEPTH_8 8 #define SPI_FIFO_DEPTH_16 16 #define SPI_FIFO_DEPTH_32 32 #define SPI_FIFO_DEPTH_64 64 #define SPI_FIFO_DEPTH_128 128 #define SPI_FIFO_DEPTH_256 256 #define BITS_ALL_SET 0xFF #define BITS_ALL_CLEAR 0x00 //err code typedef enum { /* basic errors */ SUCCESS = 0, /**< No error condition. */ PTR_ERROR = 1, /**< PTR is NULL. */ STATE_ERROR = 2, /**< status error*/ SPI_RX_FIFO_ERR = 3 /**< rx fifo setting error*/ } SPI_MASTER_ErrorCode; typedef enum { SPIM_STATE_IDLE = 0, SPIM_STATE_BUSY, SPIM_STATE_TIMEOUT, SPIM_STATE_ERROR = 0xFF }spim_status; typedef enum { SPIM_DATA_WIDTH_8BIT = 0, SPIM_DATA_WIDTH_16BIT, SPIM_DATA_WIDTH_24BIT, SPIM_DATA_WIDTH_32BIT }spim_data_width; struct spim_instance { uint32_t base_address; // spi master base address assigned uint8_t data_width; // uint8_t slave_count; // number of slave select lines uint16_t sys_clk; // system clock frequency 10-400Mhz uint16_t spi_desired_clk; // 0.01-100Mhz uint16_t clk_prescaler; // system clock divider uint16_t spi_actual_clk; // actual clock = system clock /(clock prescable x 2) uint8_t interrupts_en_bits; // TX_BUFFER_EMPTY, TX_BUFFER_NOT_FULL, // RX_BUFFER_NOT_EMPTY, RX_BUFFER_FULL uint8_t spi_clk_polarity; // SPI mode uint8_t spi_clk_phase; uint8_t spim_current_status; // IDLE, READ, WRITE, uint32_t spim_rx_fifo_afull_flag; // rx fifo almost full flag uint32_t spi_rx_fifo_depth; // depth of rx fifo uint32_t spi_tx_fifo_depth; uint32_t *spim_txbuf; //spi master transmit buffer uint32_t tx_output_cnt; //transmit count uint32_t *spim_rxbuf; //spi master receive buffer uint32_t rx_input_cnt; //receive count }; /* ***************************************************************************** * performs spi master block initialization * * Note: This function initializes the spi master block * * * Arguments: * struct spim_instance* this_spim: spi master instance * uint32_t base_addr : base address of the spi master * uint32_t spi_count : spi slave num * uint32_t prescaler : prescaler to configure the clock * uint32_t *tx_buf : buffer for data sent * uint32_t *rx_buf : buffer for data received * uint32_t spi_rx_fifo_afull_flag : rx fifo almost full flag * uint32_t spi_rx_fifo_depth : depth of rx fifo uint32_t spi_tx_fifo_depth : depth of tx fifo * * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_master_init(struct spim_instance *this_spim, uint32_t base_addr, uint8_t slave_count, uint32_t *tx_buf, uint32_t *rx_buf, uint32_t prescaler, uint32_t spi_rx_fifo_afull_flag, uint32_t spi_rx_fifo_depth, uint32_t spi_tx_fifo_depth); /* ***************************************************************************** * performs spi master block configuration * * Note: This function config the spi master block * * * Arguments: * struct spim_instance* this_spim: spi master instance * spim_data_width data_width : 00 - 8 bit * 01 - 16 bit * 10 - 24 bit * 11 - 32 bit * uint32_t prescaler : prescaler to configure the clock * * uint8_t clk_polarity : polarity of the clock * uint8_t clk_phase : clock phase * uint8_t ssnp : slave select pulse mode * uint8_t only_write : ingore read data * uint8_t spi_en : spi enable bit * uint8_t lsb_first : 0:MSB is first * 1:LSB is first * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_master_config(struct spim_instance *this_spim, spim_data_width data_width, uint32_t prescaler, uint8_t clk_polarity,uint8_t lsb_first, uint8_t clk_phase,uint8_t ssnp, uint8_t only_write ,uint8_t spi_en); /* ***************************************************************************** * performs spi master transfer operation * * Note: This function perform the spi master transfer operation in polling mode * * * Arguments: * struct spim_instance* this_spim: spi master instance * uint32_t data_buffer_out : buffer of mosi data * uint32_t byte_out_size : num of data to be sent * uint32_t data_buffer_in : buffer of mosi data * uint32_t byte_in_size : num of data to be received * * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_master_transfer_blocking(struct spim_instance *this_spim, uint32_t *data_buffer_out, uint32_t byte_out_size, uint32_t *data_buffer_in, uint32_t byte_in_size); /* ***************************************************************************** * performs spi master transfer operation * * Note: This function perform the spi master transfer operation in interrupt mode * * * Arguments: * struct spim_instance* this_spim: spi master instance * uint32_t data_buffer_out : buffer of mosi data * uint32_t byte_out_size : num of data to be sent * uint32_t byte_in_size : num of data to be received * * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_master_transfer(struct spim_instance *this_spim, uint32_t *data_buffer_out, uint32_t byte_out_size, uint32_t byte_in_size); /* ***************************************************************************** * performs spi master slave select operation * * Arguments: * struct spim_instance* this_spim: spi master instance * uint8_t enable_slave : 0:slave device not selected * 1:slave device selected * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_device_select(struct spim_instance *this_spim, uint8_t enable_slave); /* ***************************************************************************** * performs spi master slave select operation * * Arguments: * struct spim_instance* this_spim: spi master instance * uint8_t enable_slave : 0:slave device disable * 1:slave device enable * Return Value: * int: * * ***************************************************************************** */ uint8_t spi_device_enable(struct spim_instance *this_spim, uint8_t enable_slave); /* ***************************************************************************** * performs spi master interrupt function * * Note: This function perform the interrupt service routine * */ void spi_master_isr(void *ctx); #endif /*spi Master Header File*/