/* ================================================================== >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< ------------------------------------------------------------------ Copyright (c) 2019-2020 by Lattice Semiconductor Corporation ALL RIGHTS RESERVED ------------------------------------------------------------------ IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPELâ„¢ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK. Lattice grants permission to use this code pursuant to the terms of the Lattice Propel License Agreement. DISCLAIMER: LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET LICENSEE 'S REQUIREMENTS, OR THAT LICENSEE' S OPERATION OF ANY DEVICE, SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE UNINTERRUPTED OR ERROR FREE, OR THAT DEFECTS HEREIN WILL BE CORRECTED. LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE, AND RESULTS OBTAINED THEREFROM. LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT, LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE, CORRECTION, OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE SOFTWARE.IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS, EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LATTICE 'S SOLE LIABILITY, AND LICENSEE' S SOLE REMEDY, IS SET FORTH ABOVE. LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ #ifndef SMBUS_MAILBOX_H #define SMBUS_MAILBOX_H #include "sys_platform.h" // I2C STATUS #define IDLE 0x00 #define READ 0x02 #define WRITE 0x03 #define RCVD 0x04 #define IGNORE 0xFF //STATUS Responses #define DONE 0x00 #define BUSY 0xAA #define CHECKSUM_ERROR 0x55 #define NONCE_ERROR 0x77 #define BAD_CMD 0xF0 #define INVALID 0x0F #define ERROR 0xFF #define BIT(nr) (1 << (nr)) #define I2C_SLAVE_ADDRESS 0x51 #define FIFO_DEPTH 0x10 #define TX_FIFO_ALMOST_EMPTY_FLAG 0x02 #define RX_FIFO_ALMOST_FULL_FLAG 0x40 #define NACK_ADDR 0x08 #define I2C_RESET 0x04 #define CLK_STRETCH_EN 0x02 #define TX_FIFO_EN 0x20 #define STATUS_VALID 0x08 #define READ_VALID 0x18 #define TR_CMP_INT BIT(7) #define STOP_DET_INT BIT(6) #define TX_FIFO_FULL_INT BIT(5) #define TX_FIFO_AEMPTY_INT BIT(4) #define TX_FIFO_EMPTY_INT BIT(3) #define RX_FIFO_FULL_INT BIT(2) #define RX_FIFO_AFULL_INT BIT(1) #define RX_FIFO_READY_INT BIT(0) #define STOP_ERR_INT BIT(1) #define START_ERR_INT BIT(0) #define TX_FIFO_FULL BIT(5) #define TX_FIFO_AEMPTY BIT(4) #define TX_FIFO_EMPTY BIT(3) #define RX_FIFO_FULL BIT(2) #define RX_FIFO_AFUL BIT(1) #define RX_FIFO_EMPTY BIT(0) #define SMB_ALERT BIT(0) #define SMBUS_S_SHIFT 0x0 #define SMBUS_M_SHIFT 0x400 #define SMBUS_M_PRERLO (0x00) #define SMBUS_M_PRERHI (0x01*4) #define SMBUS_M_CTR (0x02*4) #define SMBUS_M_TXR (0x03*4) #define SMBUS_M_RXR (0x03*4) #define SMBUS_M_CR (0x04*4) #define SMBUS_M_SR (0x04*4) #define SMBUS_S_RD_DATA_REG (0x00) #define SMBUS_S_WR_DATA_REG (0x00) #define SMBUS_S_SLVADR_L_REG (0x04) #define SMBUS_S_SLVADR_H_REG (0x08) #define SMBUS_S_CONTROL_REG (0x0C) #define SMBUS_S_TGT_BYTE_CNT_REG (0x10) #define SMBUS_S_INT_STATUS1_REG (0x14) #define SMBUS_S_INT_ENABLE1_REG (0x18) #define SMBUS_S_INT_SET1_REG (0x1C) #define SMBUS_S_INT_STATUS2_REG (0x20) #define SMBUS_S_INT_ENABLE2_REG (0x24) #define SMBUS_S_INT_SET2_REG (0x28) #define SMBUS_S_FIFO_STATUS_REG (0x2C) struct smbus_master_instance { unsigned int base; unsigned char slave_addr; }; struct smbus_master_dev { unsigned int prerlo; unsigned int prerhi; unsigned int ctr; unsigned int txr_rxr; unsigned int cr_sr; }; // IMPORTANT: Please change the default value 0x00020000 below // to the real base address of SMBus Mailbox IP #define SMBUS_MAILBOX_RF_OFFSET 0x2000 #define SMBUS_MAILBOX_RF_ADDR (SMBUS_MAILBOX0_INST_BASE_ADDR + SMBUS_MAILBOX_RF_OFFSET) struct smbus_slave_instance { unsigned int base; unsigned int status; unsigned char *rx_buffer; unsigned char *status_buffer; unsigned int length; }; struct smbus_slave_dev { unsigned int wr_rd_data; unsigned int slvadr_l; //0x4 unsigned int slvadr_h; unsigned int control; unsigned int tgt_byte_cnt; //0x10 unsigned int int_status1; unsigned int int_enable1; unsigned int int_set1; unsigned int int_status2; //0x20 unsigned int int_enable2; unsigned int int_set2; unsigned int fifo_status; unsigned int smb_control; }; /* ***************************************************************************** * * void smbus_mailbox_write_rf(unsigned char waddr, * unsigned char wbyte) * * Write the data to Register File inside SMBus Mailbox IP. * * Arguments: * unsigned char waddr : SMBus write byte RF address. * unsigned char wbyte : SMBus write byte message data byte. * * Return Value: * none. * * ***************************************************************************** */ void smbus_mailbox_write_rf(struct smbus_slave_instance *this_smbus_slave_inst, unsigned char waddr, unsigned char wbyte); unsigned char smbus_i2c_master_init(struct smbus_master_instance *this_smbus_master_inst, unsigned int base_addr, unsigned int slave_addr); int smbus_master_write_block(struct smbus_master_instance *this_smbus_master_inst, unsigned char *data, unsigned int size); unsigned char smbus_i2c_slave_init(struct smbus_slave_instance *this_smbus_slave_inst, unsigned int base_addr, unsigned int slave_addr, unsigned int int_en); unsigned char smbus_i2c_write_data(struct smbus_slave_instance *this_smbus_slave_inst, unsigned char *buffer, unsigned int len); unsigned char smbus_i2c_alert(volatile struct smbus_slave_dev *i2c, unsigned char alert_en); void I2C_SLAVE_ISR(void *ctx); void SMBUS_SLAVE_ISR(void *ctx); #endif