SGMII GbE PCS Core

Description

Implements SGMII GbE PCS IP Core.

Devices Supported

LIFCL

References

User Guide

Revision History

1.0.0

Preliminary release.

Limitation

Known issue: There is a hold timing violation on FIFO reset port when using LSE as Synthesis Tool. It is recommended to use Synplify Pro instead to avoid this issue.