SGDMAC - Scatter Gather Direct Memory Access Controller IP core is to access main memory independent of the
processor.It offloads processor intervention.
The processor initiates transfer to SGDMAC and receives interrupt oncompletion of the transfer by DMA Engine.
The Lattice SGDMAC core implements a configurable, AXI4 - compliant DMA controller with scatter-gather capability.
LFCPNX-100, LFCPNX-50, LAV-AT-E30, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70
| 2.1.0 | Fixed an issue with CDC-related SDC constraints being dropped. Added support for Lattice Certus-NX and Avant devices and for Questasim OEM Example Design Simulation. |
| 2.0.1 | Fix an issue on AXI-S tlast and tvalid behaviour. Macros renamed and added external read/write apis. |
| 2.0.0 | Rearchitect SGDMA, enabling AXI protocol. Not backward compatible to previous versions |
| 1.2.0 | Added LFMXO5 support. |
| 1.1.0 | Added LFCPNX support. |
| 1.0.0 | Initial release. |