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#include "sgdma.h"

/*Global variable of the single and multi buffer descriptor*/
static mm2s_desc_t * mm_multi_bd_confg[MULTI_BUF_SIZE];
static s2mm_desc_t * s_multi_bd_confg[MULTI_BUF_SIZE];

/**
 * sgdma_init
 * @brief   Initialize the single and multi descriptor instances.
 *
 * @param *this_sgdma  This structure initilaize with the sgdma IP base address and number of descriptor value, have the m2s and s2mm BD address.
 * @param base_addr  This parameter specify the sgdma IP base address.
 * @param num_of_desc  This parameter specify the single or Multi Buffer descriptor value.
 * @return  None.
 */
void sgdma_init(sgdma_instance_t * this_sgdma, unsigned int base_addr, unsigned int num_of_desc)
{
	unsigned int idx = 0;

	this_sgdma->base_addr = base_addr;
	this_sgdma->num_of_desc = num_of_desc;

	for (idx = 0; idx  < this_sgdma->num_of_desc; idx++)
	{
		mm_multi_bd_confg[idx] = (mm2s_desc_t *)(this_sgdma->mm2s_bd_addr + (idx * DESC_SIZE));
		s_multi_bd_confg[idx] = (s2mm_desc_t *)(this_sgdma->s2mm_bd_addr + (idx * DESC_SIZE));
	}
}

/**
 * sgdma_reset
 * @brief   In this API reset the MM2S ctrl and S2MM cntrl register.
 *
 * @param *this_sgdma  This structure have the info of sgdma IP base address.
 * @param sgdma_cntl_type  This parameter get the mm2s control offset and s2mm control offset.
 * @return  none.
 */
void sgdma_reset(sgdma_instance_t * this_sgdma, control_type_t sgdma_cntl_type)
{
	sgdma_ctrl_reg_t * cntl_reg = (sgdma_ctrl_reg_t *)(this_sgdma->base_addr + sgdma_cntl_type);
	cntl_reg->reset = SGDMA_RESET;
}

/**
 * sgdma_irq_mask
 * @brief  Mask and unmask the mm2s and s2mm interrupt request.
 *
 * @param *this_sgdma  This structure have the info of sgdma IP base address.
 * @param sgdma_cntl_type  This parameter get the mm2s control offset and s2mm control offset.
 * @param mask_value  This parameter describe mask and unmask value.
 * @return  None.
 */
void sgdma_irq_mask(sgdma_instance_t * this_sgdma, control_type_t sgdma_cntl_type, irq_mask_t mask_value)
{
	sgdma_ctrl_reg_t * cntl_reg = (sgdma_ctrl_reg_t *)(this_sgdma->base_addr + sgdma_cntl_type);
	cntl_reg->cmpl_irq_mask = mask_value;
}

/**
 * get_sgdma_reg_status
 * @brief  Get the mm2s and s2mm register status , bd len err, xfer_cmpl , xfer_err inforamtion.
 *
 * @param *this_sgdma  This structure have the info of sgdma IP base address.
 * @param sgdma_sts_type  This parameter get the mm2s status offset and s2mm status offset as a parameter.
 * @return  This API return the mm2s status register address.
 */
sgdma_sts_reg_t * get_sgdma_reg_status(sgdma_instance_t * this_sgdma, status_type_t sgdma_sts_type)
{
	sgdma_sts_reg_t *sts_reg = (sgdma_sts_reg_t *)(this_sgdma->base_addr + sgdma_sts_type);
	return sts_reg;
}

/**
 * get_mm2s_bd_status
 * @brief  Get the mm2s BD status transffered len err, cmpl , slave_err ,descriptor error inforamtion.
 *
 * @param idx  This parameter defines the number of multiple buffer descriptor sequences.
 * @return  This API return the mm2s status register value.
 */
unsigned int get_mm2s_bd_status(int idx)
{
	return mm_multi_bd_confg[idx]->mm_bd_ext.mm_status;
}

/**
 * get_s2mm_bd_status
 * @brief  Get the s2mm BD status transffered len err, cmpl , slave_err ,descriptor error inforamtion.
 *
 * @param idx  This parameter defines the number of multiple buffer descriptor sequences.
 * @return  This API return the s2mm status register value.
 */
unsigned int get_s2mm_bd_status(int idx)
{
	return s_multi_bd_confg[idx]->s_bd_ext.s_status;
}

/**
 * mm2s_buf_desc_dma
 * @brief   Performs a mm2s_buf_desc_dma API configure single and multiple buffer descriptor to update the registers value and trigger the DMA.
 *
 * @param *this_sgdma  This structure parameter have the info of base address of mm2s buffer, length and number of descriptor.
 * length is specify the buffer length and num_of_desc is specify the single or multiple buffer descriptor value.
 *
 * @return  This API returns 0 on success 1 on failure.
 */
unsigned int mm2s_buf_desc_dma(sgdma_instance_t * this_sgdma)
{
	unsigned int idx = 0;
	volatile unsigned int * mm_multi_wr_reg_value = (unsigned int *)(this_sgdma->base_addr + MM2S_CURDESC);
	volatile unsigned int * mm_multi_rd_sts_reg_value = (unsigned int *)(this_sgdma->base_addr + MM2S_STS);
	mm2s_ctrl_reg_t * cntl_reg = (mm2s_ctrl_reg_t *)(this_sgdma->base_addr + MM2S_CTRL);

	for(idx = 0; idx < this_sgdma->num_of_desc; idx++)
	{
		mm_multi_bd_confg[idx]->mm_bd_ext.mm_buffer_addr = (unsigned int)(this_sgdma->buffer + ((idx * this_sgdma->per_desc_length) >> 2));
		mm_multi_bd_confg[idx]->mm_bd_ext.mm_buffer_msb_addr = MSB_ADDR;

		//Control
		if (this_sgdma->per_desc_length < MAX_TRANSFER_SIZE)
		{
			if(idx == (this_sgdma->num_of_desc - 1))
			{
				mm_multi_bd_confg[idx]->mm_bd_ext.mm_control = (NXT_0 << NXT_BIT_POSITION)|(FP_0 << FP_BIT_POSITION)|(BUFFER_SIZE_MASK & this_sgdma->per_desc_length);
			}
			else
			{
				mm_multi_bd_confg[idx]->mm_bd_ext.mm_control = (NXT_1 << NXT_BIT_POSITION)|(FP_0 << FP_BIT_POSITION)|(BUFFER_SIZE_MASK & this_sgdma->per_desc_length);
			}
		}
		else
		{
			return FAILURE;
		}
	}

	//MM2S_CURDESC
	*mm_multi_wr_reg_value =  (unsigned int)mm_multi_bd_confg[IDX_0];
	//DMA trigger
	cntl_reg->mm_request = DMA_TRIGGER;

	if(this_sgdma->blocking_mm2s == TRUE)
	{
		while(!(*mm_multi_rd_sts_reg_value >> XFER_CMPL_POSITION) & XFER_CMPL_1);
	}

	return SUCCESS;
}

/**
 * s2mm_buf_desc_dma
 * @brief  Performs a s2mm_buf_desc_dma API configure single and multiple buffer descriptor to update the registers value and trigger the DMA.
 *
 * @param *this_sgdma  This structure parameter have the info of base address of s2mm buffer, length and number of descriptor.
 * length is specify the buffer length and num_of_desc is specify the single or multiple buffer descriptor value.
 *
 *
 * @return  This API returns 0 on success and 1 for failure.
 */
unsigned int s2mm_buf_desc_dma(sgdma_instance_t * this_sgdma)
{
	unsigned int idx = 0;
	volatile unsigned int * s_multi_wr_reg_value = (unsigned int *)(this_sgdma->base_addr + S2MM_CURDESC);
	volatile unsigned int * s_multi_rd_sts_reg_value = (unsigned int *)(this_sgdma->base_addr + S2MM_STS);
	s2mm_ctrl_reg_t * cntl_reg = (s2mm_ctrl_reg_t *)(this_sgdma->base_addr + S2MM_CTRL);

	for(idx = 0; idx < this_sgdma->num_of_desc; idx++)
	{
		s_multi_bd_confg[idx]->s_bd_ext.s_buffer_addr = (unsigned int)(this_sgdma->buffer + ((idx * this_sgdma->per_desc_length ) >> 2));
		s_multi_bd_confg[idx]->s_bd_ext.s_buffer_msb_addr = MSB_ADDR;
		//Control
		if (this_sgdma->per_desc_length < MAX_TRANSFER_SIZE)
		{
			if(idx == (this_sgdma->num_of_desc - 1))
			{
				s_multi_bd_confg[idx]->s_bd_ext.s_control = (NXT_0 << NXT_BIT_POSITION)|(FP_0 << FP_BIT_POSITION)|(BUFFER_SIZE_MASK & this_sgdma->per_desc_length);
			}
			else
			{
				s_multi_bd_confg[idx]->s_bd_ext.s_control = (NXT_1 << NXT_BIT_POSITION)|(BUFFER_SIZE_MASK & this_sgdma->per_desc_length);
			}
		}
		else
		{
			return FAILURE;
		}
	}

	//S2MM_CURDESC
	*s_multi_wr_reg_value =  (unsigned int)s_multi_bd_confg[IDX_0];
	//DMA trigger
	cntl_reg->s_request = DMA_TRIGGER;

	if(this_sgdma->blocking_s2mm == TRUE)
	{
		while(!(*s_multi_rd_sts_reg_value >> XFER_CMPL_POSITION) & XFER_CMPL_1);
	}

	return SUCCESS;
}