RISC-V SM CPU

Description

RISC-V SM CPU with PIC and Timer

Devices Supported

LAV-AT, MachXO2, MachXO3, MachXO3D, LIFCL-40, LIFCL-17, LIFCL-33, LFD2NX-40, LFCPNX-100, LFMXO5-25, LFE5UM-45F

References

Revision History

1.6.1

Fix Interrupt Request Interface Number GUI bug

1.6.0

MISA support

Support LFE5UM-45F device

Version Number Alignment

1.5.0 Add soft JTAG for all platforms
1.4.0

Add Avant support

Enable debug module for Avant family

1.3.0 Routine support
1.2.0 Support LIFCL-33
1.1.0 Support LFMXO5 and LFCPNX
1.0.0 Release for Propel 2.1