/*   ==================================================================

     >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
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     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™
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       Lattice grants permission to use this code pursuant to the
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     ================================================================== */

#ifndef BSP_DRIVER_RISCV_RISCV_H__
#define BSP_DRIVER_RISCV_RISCV_H__


#include <stdio.h>
typedef uint32_t reg_t;


#define MCAUSE_VAL_MASK 0xF
#define MCAUSE_VAL_MEIP 11
#define MCAUSE_VAL_SEIP 9
#define MCAUSE_VAL_MTIP 7
#define MCAUSE_VAL_STIP 5
#define MCAUSE_VAL_MSIP 3

#define MIE_VAL_USIE 0x001		// U mode Soft INT
#define MIE_VAL_SSIE 0x002		// S mode Soft INT
#define MIE_VAL_MSIE 0x008		// M mode Soft INT
#define MIE_VAL_UTIE 0x010		// U mode Timer INT
#define MIE_VAL_STIE 0x020		// S mode Timer INT
#define MIE_VAL_MTIE 0x080		// M mode Timer INT
#define MIE_VAL_UEIE 0x100		// U mode External INT
#define MIE_VAL_SEIE 0x200		// S mode External INT
#define MIE_VAL_MEIE 0x800		// M mode External INT


#define THIS_HART (r_tp())
static inline reg_t r_tp()
{
	reg_t x;
	asm volatile("mv %0, tp" : "=r" (x) );
	return x;
}


static inline reg_t r_mhartid()
{
	reg_t x;
	asm volatile("csrr %0, mhartid" : "=r" (x) );
	return x;
}


/* Machine Status Register, mstatus */
#define MSTATUS_MPP (3 << 11)
#define MSTATUS_SPP (1 << 8)

#define MSTATUS_MPIE (1 << 7)
#define MSTATUS_SPIE (1 << 5)
#define MSTATUS_UPIE (1 << 4)

#define MSTATUS_MIE (1 << 3)
#define MSTATUS_SIE (1 << 1)
#define MSTATUS_UIE (1 << 0)


static inline reg_t r_mstatus()
{
	reg_t x;
	asm volatile("csrr %0, mstatus" : "=r" (x) );
	return x;
}

static inline void w_mstatus(reg_t x)
{
	asm volatile("csrw mstatus, %0" : : "r" (x));
}

/*
 * machine exception program counter, holds the
 * instruction address to which a return from
 * exception will go.
 */
static inline void w_mepc(reg_t x)
{
	asm volatile("csrw mepc, %0" : : "r" (x));
}

static inline reg_t r_mepc()
{
	reg_t x;
	asm volatile("csrr %0, mepc" : "=r" (x));
	return x;
}

/* Machine Scratch register, for early trap handler */
static inline void w_mscratch(reg_t x)
{
	asm volatile("csrw mscratch, %0" : : "r" (x));
}

/* Machine-mode interrupt vector */
static inline void w_mtvec(reg_t x)
{
	asm volatile("csrw mtvec, %0" : : "r" (x));
}

/* Machine-mode Interrupt Enable */
#define MIE_MEIE (1 << 11) // external
#define MIE_MTIE (1 << 7)  // timer
#define MIE_MSIE (1 << 3)  // software

static inline reg_t r_mie()
{
	reg_t x;
	asm volatile("csrr %0, mie" : "=r" (x) );
	return x;
}

static inline void w_mie(reg_t x)
{
	asm volatile("csrw mie, %0" : : "r" (x));
}

static inline reg_t r_mcause()
{
	reg_t x;
	asm volatile("csrr %0, mcause" : "=r" (x) );
	return x;
}

static inline reg_t r_mideleg()
{
	reg_t x;
	asm volatile("csrr %0, mideleg" : "=r" (x) );
	return x;
}

static inline void w_mideleg(reg_t x)
{
	asm volatile("csrw mideleg, %0" : : "r" (x));
}

/*Supervisor mode*/
#define MIDELEG_SSIP (1 << 1)
#define MIDELEG_STIP (1 << 5)
#define MIDELEG_SEIP (1 << 9)

#define SSTATUS_SPP (1 << 8)
#define SSTATUS_SPIE (1 << 5)
#define SSTATUS_UPIE (1 << 4)
#define SSTATUS_SIE (1 << 1)
#define SSTATUS_UIE (1 << 0)

#define SIE_SEIE (1 << 9) // external
#define SIE_STIE (1 << 5)  // timer
#define SIE_SSIE (1 << 1)  // software

static inline reg_t r_sie()
{
	reg_t x;
	asm volatile("csrr %0, sie" : "=r" (x) );
	return x;
}

static inline void w_sie(reg_t x)
{
	asm volatile("csrw sie, %0" : : "r" (x));
}

static inline reg_t r_scause()
{
	reg_t x;
	asm volatile("csrr %0, scause" : "=r" (x) );
	return x;
}

static inline reg_t r_sstatus()
{
	reg_t x;
	asm volatile("csrr %0, sstatus" : "=r" (x) );
	return x;
}

static inline void w_sstatus(reg_t x)
{
	asm volatile("csrw sstatus, %0" : : "r" (x));
}

static inline void w_sepc(reg_t x)
{
	asm volatile("csrw sepc, %0" : : "r" (x));
}

static inline reg_t r_sepc()
{
	reg_t x;
	asm volatile("csrr %0, sepc" : "=r" (x));
	return x;
}

static inline void w_stvec(reg_t x)
{
	asm volatile("csrw stvec, %0" : : "r" (x));
}


static inline void interrupt_enable(uint32_t mask) 
{
	w_mie(r_mie() | mask);
}


static inline void interrupt_disable(uint32_t mask)
{
	w_mie(r_mie() & ~mask);
}

#endif /* BSP_DRIVER_RISCV_RISCV_H__ */