RISC-V MC CPU with optional Cache, PIC and Timer
LAV-AT, MachXO2, MachXO3, MachXO3D, LIFCL-40, LIFCL-17, LIFCL-33, LFD2NX-40, LFCPNX-100, LFMXO5-25
| 2.5.0 | Enable debug module for all Platforms Add mcycle and minstret for cores without cache Add instructions to flush data cache |
| 2.4.0 | Enable debug module for Avant family |
| 2.3.0 | Disable debug module for Avant Performance enhancement Fix vectored interrupt mode for cache cores Simulation mode and debug mode cannot be selected together |
| 2.2.2 | Cache core optimization |
| 2.2.1 | Fix debug related issues for cache cores |
| 2.2.0 | Support LIFCL-33 |