QSPI Flash Controller

Description:

The Lattice QSPI Flash Controller IP core supports the SPI, DSPI, and QSPI protocols to perform operations on the target flash device.

A Quad Serial Peripheral Interface (QSPI) is a four-tri-state data line serial interface that is commonly used to program, erase, and read SPI Flash memories. QSPI enhances the throughput of a standard SPI by four times since four bits are transferred every clock cycle.

A Dual Serial Peripheral Interface (DSPI) uses two tri-state data lines and is used to program, erase, and read SPI flash memories. DSPI transfers two bits with every clock cycle.

A Standard Serial Peripheral Interface (SPI) uses separate data lines for input and output to perform flash operations.

Devices Supported

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5, Lattice Avant, Certus-N2

References

Release Notes

1.4.0
  • IP Release Notes
    		•
    1.3.0 Added LIFCL, LFMXO5 and LN2-CT device support.
     Added XiP pattern IP GUI attribute.
     Transmit and receive FIFO features are already supported.
     Added generic command feature support to enable XiP of other flash devices.
     Supported AXI4 multiple bursts for direct read access.
    1.2.0 Added AXI4 direct access and XiP for Macronix features support.
     Updated interrupt signal.
     Updated IP driver.
    1.1.5 Updated AHB-L direct access feature implementation.
    1.1.4 Added LFD2NX device support.
     Added AHB-L direct access feature support.
    1.1.3 Added LAV-AT device support.
     Added multiple SPI target feature support.
     Updated IP GUI and registers.
     Updated implementation of supported commands with varying command, address and data IO lanes on SPI interface.
     Updated customer testbench.
    1.1.2 Fixed SPI clock and data alignment.
     Updated supported commands feature implementation.
    1.1.1 Updated IP driver.
    1.1.0 Added LFCPNX device support.
    1.0.0 Initial release.