| 2.0.0 |
PHY Configuration
- Increased aggregation and bifurcation up to x8 lanes
- Increased data rates of 8.0 Gbps, and 16.0 Gbps
- Added 128b/130b encoding at 8 Gbps and 16 Gbps
- Added support for PCIe L1-substate power management and Separate RefClk Independent SSC Architecture (SRIS)
Hard IP Link Layer Features
- PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications
- Backward compatible with PCI Express 3.x, 2.x, 1.x
- x8 PCI Express Lanes with support for bifurcation
- Supported lane configurations:
- 1 × 8, 1 × 4, 1 × 2, 1 × 1
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| 1.1.0 |
PHY Configuration
- Aggregation and bifurcation up to x4 lanes
- Data rates of 2.5 Gbps, 5.0 Gbps
- Selectable parallel data widths such as 8, 16, 32, 64
- 8b/10b encoding at 2.5 Gbps and 5 Gbps
- Adaptive and configurable RX Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE)
- Adaptive and programmable TX equalization
- Extensive PMA debug capability via read/write and read-only registers in PCS
- Register-based control of all PCS-to-PMA signals
- A wide range of reference clock frequencies with optional fractional frequency correction capability
- A wide range of divided clock frequencies for external-to-PHY usage with optional spread-spectrum clock (SSC) capability
- Built-in, on-chip SSC generation and full configuration from –5000 to +5000 ppm
- Test support features such as near-end loopback, PLL bypass modes, and others
- Protocol-compatible features such as LOS, squelch, power modes, and others
Hard IP Link Layer Features
- PCI Express Base Specification Revision 2.0 compliant including compliance with earlier PCI Express Specifications
- Backward compatible with PCI Express 1.x
- x4 PCI Express Lanes with support for bifurcation
- Supported lane configurations:
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