PCI Express for CertusPro-NX IP Core, previously named PCIE_X4, is a high speed serial IO interface that supports 2.5 GT/s, 5.0 GT/s and 8.0 GT/s data rates.
This IP Core supports Endpoint mode with up to 4 lanes and 256 bits user interface.
Bifurcation options can support up to two Links with Link and Lane configurations such as 1x4, 1x2, 1x1, 1x2+1x1 and 1x1+x1.
Multi-function is supported (each Link) with up to 4 physical functions for Endpoint mode.
CertusPro-NX, MachXO5T-NX (LFMXO5-55T, LFMXO5-100T), MachXO5D-NX (LFMXO5-55TD)
| 3.2.0 | IP Release Notes |
| 3.1.0 |
High Performance PCIe DMA for PCIe Gen3x4 tested on CertusPro-NX Bridge Board. High Performance PCIe DMA for PCIe Gen3x4 Demo driver included as part of IP Package. |
| 3.0.0 |
High Performance PCIe DMA for PCIe Gen3x4. PCIe DMA: Supports AXI-MM interface on user application. PCIe DMA: Supports Descriptor Prefetching for performance improvement. PCIe DMA: Supports MSI interrupt when DMA transfer is completed. PCIe DMA: Example Design simulation supported. |
| 2.4.1 | Fixed MachX05T-NX/MachX05D-NX GUI issue. |
| 2.4.0 |
Enable Propel support. Fixed issue where gen3x1 simtime is slower than gen3x4. Fixed timing constraint issues not read in properly in encrypted RTL. Fixed Link1 PF config issue. Fixed sd_ext_1_refclk_i issue. Warnings fix. |
| 2.3.1 | Reduced simtime for Modelsim OEM simulator |
| 2.2.0 |
Updated for Gen1/2/3 Endpoint with DMA x1, x2 and x4 support Updated user data interface to 64, 128 and 256 bits but clock frequency is half of sys_clk Updated Maximum descriptor block size supported to 4 KB. Supported 125 MHz PHY refclk Added mixed mode support Added example design for simulation |
| 2.1.0 | Updated for Gen3 Endpoint with DMA 1x1 support |
| 2.0.0 | Optimized for Gen3 Endpoint with DMA 1x4 support |
| 1.1.0 | Added Enpoint DMA 1x4 function and Root Port Mode |
| 1.0.1 | Initial release. |