/*   ==================================================================
 
     >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2024 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------
 
     DISCLAIMER:
 
    LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS,
    WHETHER EXPRESSED, IMPLIED, STATUTORY,
    OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR
    COMMUNICATION WITH LICENSEE,
    AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF
    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
    LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET
    LICENSEE 'S REQUIREMENTS, OR THAT LICENSEE' S OPERATION OF ANY DEVICE,
    SOFTWARE OR SYSTEM USING THIS FILE OR ITS CONTENTS WILL BE
    UNINTERRUPTED OR ERROR FREE,
    OR THAT DEFECTS HEREIN WILL BE CORRECTED.
    LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE
    ITS INTENDED RESULTS, AND FOR THE PROPER INSTALLATION, USE,
    AND RESULTS OBTAINED THEREFROM.
    LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING
    DEFECTIVE OR FAILING TO PERFORM PROPERLY AND IN SUCH EVENT,
    LICENSEE SHALL ASSUME THE ENTIRE COST AND RISK OF ANY REPAIR, SERVICE,
    CORRECTION,
    OR ANY OTHER LIABILITIES OR DAMAGES CAUSED BY OR ASSOCIATED WITH THE
    SOFTWARE.IN NO EVENT SHALL LATTICE BE LIABLE TO ANY PARTY FOR DIRECT,
    INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
    INCLUDING LOST PROFITS,
    ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS,
    EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    LATTICE 'S SOLE LIABILITY, AND LICENSEE' S SOLE REMEDY,
    IS SET FORTH ABOVE.
    LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE,
    ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES'
    INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER' S
    RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND
    FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS.
     ------------------------------------------------------------------
 
     ================================================================== */

#ifndef __PCIE_DMA_REGS_H__
#define __PCIE_DMA_REGS_H__
/*Register Offsets*/
/* Register name, address and offset */
#define H2F_DMA_CTRL					0x0
#define H2F_DMA_STS					    0x0C
#define H2F_CPLT_DESC_COUNT				0x18

#define F2H_DMA_CTRL					0x100
#define F2H_DMA_STS					    0x10C
#define F2H_CPLT_DESC_COUNT				0x118

#define H2F_DESC_ADDR_LOW				0x200
#define H2F_DESC_ADDR_HIGH				0x204
#define H2F_CONT_REMAIN 				0x208

#define F2H_DESC_ADDR_LOW				0x300
#define F2H_DESC_ADDR_HIGH				0x304
#define F2H_CONT_REMAIN 				0x308

#define INT_MODE        				0x400
#define H2F_INT_VEC     				0x404
#define F2H_INT_VEC      				0x408
#define H2F_INT_IP                      0X40C

#define PLACEHOLDER_SRC_ADDR        0x10000
#define CONT_DESC_SHIFT             0x8  
#define INT_SHIFT                   0x1            
#define INT_ENABLE                  0x1
#define INT_NOT_ENABLE              0x0
#define NOT_EOP                     0x0
#define EOP                         0x1
#define START_DMA                   0x1
#define START_DMA_MASK              0x1
#define START_DMA_IS_CLEAR          0x0
#define BUSY                        0x1
#define CHAN0_H2F_INT_WIRE          0x0
#define CHAN0_H2F_INT_INTX          0x1
#define CHAN0_F2H_INT_WIRE          0x00000
#define CHAN0_F2H_INT_INTX          0x10000
#define CHAN0_INTA                  0x0
#define CHAN0_INTB                  0x1
#define CHAN0_INTC                  0x2
#define CHAN0_INTD                  0x3
#define CHAN0_MSI_VECT_0            0x0
#define CHAN0_MSI_VECT_1            0x1

#endif   // #ifndef __PCIE_DMA_REGS_H__