PCI Express X1 (PCIE_X1) IP Core is a high speed serial IO interface that supports 2.5 GT/s and 5.0 GT/s data rates.
This IP Core supports both Endpoint and Root Port mode with x1 lane and 32 bits user interface.
Multi-function is supported with up to 4 physical functions for Endpoint mode.
LIFCL-40,LFD2NX-40
| 1.2.2 | Added ED Testbench. |
| 1.2.1 | Added Address Space mapping for Propel. |
| 1.2.0 | Added Propel support. |
| 1.1.3 | Updated for Linux support. |
| 1.1.2 |
Updated IP GUI. Fixed several issues on DMA. Added DMA data checking on TB. |
| 1.1.1 | Fix issue on path with space character in component generator script. |
| 1.1.0 |
Added Root Port mode. Added LFD2NX-40. |
| 1.0.2 | Corrected aux_clk_i connection on default interface. |
| 1.0.1 | Initial release. |
| 1.0.0 | Preliminary release. |