Multi-Port Arbiter for DDR3 Memory Controller

Description

The Multi-Port Arbiter for DDR3 Memory Controller IP core is a general purpose memory controller
which provides a generic command interface to user applications that generates
the Memory access commands with the inputs provided from multi users(AHB interface).

Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100

References

• User Guide

Revision History