LPDDR4 Memory Controller for Nexus Devices

Description

The Lattice Semiconductor Memory controller Interface Module provides a solution to interface to LPDDR4 Memory standard. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

Features:

LPDDR4 Memory Controller is compliant to JESD209-4C SDRAM standards
Speeds of up to 533 MHz command or data speeds of 1066 MTps
DDR widths of x16, x32, and x64
Burst length BL16/32 OTF
Command frequency: 300, 350, 400, and 533 MHz
8:1 (X4) gearing mode
Configurable address widths to support various densities
AXI4 interface support of 1 to 64 burst length, aligned addressing to AxSIZE only
Unaligned transfer support using byte strobe
Periodic training support
- Automatic programmable interval refresh
- ZQ calibration
- Temperature tracking for LPDDR4
- Adaptive/derate refresh rate for extended temperature support LPDDR4
Special features
- Reliability support SEC DED ECC
- Low power features DBI for LPDDR4
- Automatic detection of idle triggering SREF entry
- Dynamic On-Die Termination (ODT) controls
- Polling and Out-of-band Interrupt support for error and extended temperature support
Training and initialization support
- Automatic SDRAM initialization
- CA_VREF training for LPDDR4(future enhancement)
- Write leveling support
- DQ-DQS skew optimization for Write training
- Dynamic valid window optimization (Read and Write Path)
- Memory Controller DQ_VREF training(future enhancement)
- Memory DQ_VREF training (future enhancement)

Devices Supported

LFCPNX-100, LFCPNX-100AUTODIE, LFCPNX-50, LFMXO5-55T, LFMXO5-100T

References

Revision History

2.3.1	Updated driver to add NOP delay when polling for training done. Disable dual rank option for 533MHz.
2.3.0	Added driver support.
2.2.0	Reduce AXI4 Read Latency. Added Dual Rank support. Added ODT programming support. Added Automatic Vref Training support. Fix write-read ordering issue when write queue is full. Added support for LFCPNX-100AUTODIE device.
2.1.0	Added support for random AXI4 strobe. Added support for AXI4 data width less than DDR data width * 8. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
2.0.2	Supported random AXI4 burst length from 1 to 64 beats. Supported any combination of burst length and burst size.
2.0.1	Fixed Single access issues. Added Enable APB I/F option in the GUI. Enabled the No. of Outstanding Refresh Option and set the default value to 8. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
2.0.0	Replace AHB-Lite and Native I/F with AXI4. Improve performance up to >80% DDR bus efficiency. Implemented Partial encryption to enable constraint propagation. Added 300MHz and 350MHz support. Validated all supported DDR clock frequencies on the board. Only Synplify Pro is supported for this version. The IP fails on the board using LSE.
1.3.0	Added Vref training support for CA Vref, Controller's DQ Vref, and Memory DQ Vref. Improved Read performance for Native I/F. Added testbench for running simulation. Removed DDR3 support for this Memory Controller IP. Updated GUI options: ECC is fixed to Disabled, Internal RISC-V CPU is fixed to Enabled.
1.2.1	Added limitation for DDR3. The DDR Interface Type GUI option has been fixed to LPDDR4.
1.2.0	Updated for Radiant 3.1. Updated eval files to add the design for testing the IP on the board. Updated training logic to work on the board. Added Native I/F local data bus.
1.1.0	Updated for Radiant 3.0. Added support for Micron WDQS Control Mode 2.
1.0.0	Initial release.