Memory Controller

Description

The Lattice Semiconductor Memory controller Interface Module provides a solution to interface to DDR3 or LPDDR4 DDR Memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

Features:

• Memory Controller supports LPDDR4, compliant to JESD209-4 SDRAM standards
• Speeds of up to 533 MHz command or data speeds of 1066 MTps
• DDR widths of x16, x32, and x64
• Burst length BL16/32 OTF
• Command frequency: 400, and 533 MHz
• 8:1 (X4) gearing mode
• Configurable address widths to support various densities
• AHB-Lite interface support of Single INCR4, WRAP4, and INCR8 for read transaction types
• AHB-Lite interface support of Single INCR4, and INCR8 for write transaction types
• Native interface support of INCR1, INCR2, and INCR4 for read transaction types
• Native interface support of INCR1, INCR2, and INCR4 for write transaction types
• Periodic training support
  • Automatic programmable interval refresh
  • ZQ calibration
  • Temperature tracking for LPDDR4
  • Adaptive/derate refresh rate for extended temperature support LPDDR4
• Special features
  • Reliability support SEC DED ECC
  • Low power features DBI for LPDDR4
  • Automatic detection of idle triggering SREF entry
  • Dynamic On-Die Termination (ODT) controls
  • Polling and Out-of-band Interrupt support for error and extended temperature support
• Training and initialization support
  • Automatic SDRAM initialization
  • CA/VREF training for LPDDR4
  • Write leveling support
  • DQ-DQS skew optimization for Write training
  • Dynamic valid window optimization (Read and Write Path)

Devices Supported

LFCPNX-100

References

• User Guide

Revision History