Memory_Controller_for_Avant_Devices

Description

The Lattice Semiconductor Memory controller Interface Module provides a solution to interface to LPDDR4 DDR Memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

Features:

Memory Controller supports LPDDR4, compliant to JESD209-4 SDRAM standards
Speeds of up to 800 MHz command or data rates of 1600 MTps
DDR widths of x16, x32, and x64
Burst length BL16/32 OTF
Command frequency: 266, 300, 350, 400, 533, 666, and 800 MHz
8:1 (X4) gearing mode
Configurable address widths to support various densities
AXI4 interface support of 1 to 64 burst length.
AXI4 unaligned transfer support with WRSTRB, the address must be aligned to AxSIZE.
Periodic training support
- Automatic programmable interval refresh
- ZQ calibration
- Temperature tracking for LPDDR4
- Adaptive/derate refresh rate for extended temperature support LPDDR4
Special features
- Low power features DBI
- Automatic detection of idle triggering SREF entry
Training and initialization support
- Automatic SDRAM initialization
- CA_VREF training for LPDDR4
- Write leveling support
- DQ-DQS skew optimization for Write training
- Dynamic valid window optimization (Read and Write Path)

Devices Supported

LAV-AT-E70, LAV-AT-G70, LAV-AT-X70

References

User Guide

Revision History

1.3.0	Added support for LAV-AT-G70 and LAV-AT-X70 devices. Validated 350, 400, 533, 666, 800MHz, 933MHz, and 1066MHz on the board. Reduce AXI4 read Latency for long burst. Increase Maximum burst length up to 256 based on the IP GUI setting. Added powerdown support. Only Synplify Pro is supported for this version, LSE is not supported.
1.2.0	Enhance AXI4 I/F to support: Burst length from 1 to 64 beats Any combination of burst length and burst size Unaligned transfer using WSTRB AXI4 data width less than DDR data width * 8 Validated 266, 300, 350, 400, 533, 666 and 800MHz on the board. Added PHY-side and DRAM-side DQ_VREF training support. Disabled powerdown support for this version.
1.1.0	Added support for DDR clock frequency != 800MHz. Enabled Post-Synthesis and Post-PAR simulations. Validated at 533MHz DDR clock, will validate other frequencies in next release.
1.0.0	Initial release.