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IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ /** * @file : This file is used to initialize the i3c target and configure it. */ #ifndef i3c_target_H_ #define i3c_target_H_ /* Driver Details */ #define I3C_TARGET_DRV_VER "v1.0.0" /* REGISTER OPTION AND SECONDARY CONTROLLER*/ #define REG32_BIT 1 #define REG8_BIT 0 #define SECONDARY_CONTROLLER_ENABLE 0 // set it 0 when target is acts as target and set it 1 when target acts as secondary controller /* REGISTER BITS USED IN THE CODE FOR SET AND RESET */ #define SET_TGT 1 #define RESET 0 /* REGISTER BITS USED IN THE CODE FOR SUCCESS AND FAILURE */ #define SUCCESS 1 #define FAILURE 0 /* REGISTER BITS USED IN THE CODE IN INITIALIZATION OF TARGET */ #define ZERO 0 #define CLEAR 0x00 #define INTERRUPT_ENABLE 0xFF /* REGISTER BITS USED IN THE CODE FOR READ AND WRITE*/ #define EIGHT_BIT 8 #define TX_FIFO_FULL_TGT 0x80 #define RX_FIFO_FULL 0x20 #define RXFIFO_NOTEMPTY 0x40 /* REGISTER BITS USED IN THE CODE FOR HOT JOIN */ #define EC_REQ_HJIN 0x08 #define HJ_CAPABLE 0x08 #define HJ_ENABLE 0x08 #define BUSAVL 0x02 #define BUSIDLE 0x01 #define EC_REQ_HJ 0x08 #define HJ_REQ_STATUS 0x80 #define HJ_NACK 0x20 #define HJ_DONE 0x40 /* REGISTER BITS USED IN THE CODE FOR IBI */ #define RST_TXFIFO 0x04 #define IBI_CAPABLE 0x01 #define IBI_ENABLE 0x01 #define EC_REQ_IBI 0x01 #define IBI_REQ_STATUS 0x08 #define IBI_NACK 0x02 #define BCR_BIT2 0x04 #define IBI_DONE 0x04 #define IBI_PAYLD_ERR 0x01 /* REGISTER BITS USED IN THE CODE FOR SECONDARY CONTROLLER REQUEST */ #define EC_EN_CNTRL_ROLE 0x02 #define CNTRL_REQ 0x02 #define CNTRL_REQ_GEN 0x08 #define CNTRL_REQ_NACK 0x02 #define CNTRL_ROLE_DONE 0x04 /* REGISTER BITS USED IN THE CODE FOR FIFO LOOP BACK */ #define FIFO_LOOPBACK_EN 0x10 /* * ------------------------------------------------------ - - - I3C Target Register-map - - - ------------------------------------------------------ */ #if REG32_BIT typedef struct { #if SECONDARY_CONTROLLER_ENABLE //used for secondary controller connection volatile unsigned int reserved[128]; #endif volatile unsigned int bcr; //00 volatile unsigned int dcr; volatile unsigned int dyn_addr; volatile unsigned int event_command_en; volatile unsigned int event_command_dev_config; volatile unsigned int event_command_req; //05 volatile unsigned int hj_ibi_retry; volatile unsigned int max_wr_legth_msb; volatile unsigned int max_wr_legth_lsb; volatile unsigned int max_rd_legth_msb; volatile unsigned int max_rd_legth_lsb; //A volatile unsigned int max_ibi_payload; volatile unsigned int max_wr_data_speed; volatile unsigned int max_rd_data_spped; volatile unsigned int max_rd_turnout_time_msb; volatile unsigned int max_rd_turnout_time; //F volatile unsigned int max_rd_turnout_time_lsb; volatile unsigned int dev_provisioned_id6; volatile unsigned int dev_provisioned_id5; volatile unsigned int dev_provisioned_id4; //13 volatile unsigned int dev_provisioned_id3; volatile unsigned int dev_provisioned_id2; volatile unsigned int dev_provisioned_id1; volatile unsigned int static_addr; //17 volatile unsigned int dev_capabilities_byte1; volatile unsigned int dev_capabilities_byte2; volatile unsigned int dev_capabilities_byte3; volatile unsigned int reserved1; volatile unsigned int osc_inacc; volatile unsigned int reserved2; volatile unsigned int reserved3; volatile unsigned int reserved4; volatile unsigned int rx_fifo; //20 volatile unsigned int reserved5; volatile unsigned int tx_fifo; //22 volatile unsigned int reserved6; volatile unsigned int reserved7; volatile unsigned int reserved8; volatile unsigned int reserved9; volatile unsigned int reserved10; volatile unsigned int soft_reset; volatile unsigned int target_response; //29 volatile unsigned int get_status_msb; volatile unsigned int get_status_lsb; volatile unsigned int bus_activity_state; volatile unsigned int tgt_reaction_action_1; volatile unsigned int tgt_reaction_action_2; volatile unsigned int tgt_reaction_action_3; //2F volatile unsigned int interrupt_1; volatile unsigned int interrupt_1_en; //31 volatile unsigned int interrupt_1_set; volatile unsigned int interrupt_2; volatile unsigned int interrupt_2_en; //34 volatile unsigned int interrupt_2_set; //35 volatile unsigned int interrupt_3; //36 volatile unsigned int interrupt_3_en; volatile unsigned int interrupt_3_set; volatile unsigned int interrupt_4; //39 volatile unsigned int interrupt_4_en; volatile unsigned int interrupt_4_set; volatile unsigned int interrupt_5; //3C volatile unsigned int interrupt_5_en; volatile unsigned int interrupt_5_set; //3E volatile unsigned int reserved11; volatile unsigned int deftgts_count; //40 volatile unsigned int deftgtsrxfifo_start; volatile unsigned int deftgtsrxfifo_count; volatile unsigned int controller_role_handoff; volatile unsigned int getmxds_con_cap; volatile unsigned int getmxds_con_cap_lsb; //45 volatile unsigned int getmxds_con_cap1; //46 volatile unsigned int getmxds_con_cap2; volatile unsigned int reserved12; volatile unsigned int reserved13; volatile unsigned int reserved14; volatile unsigned int reserved15; //4A volatile unsigned int reserved16; volatile unsigned int reserved17; volatile unsigned int reserved18; volatile unsigned int reserved19; volatile unsigned int bus_mode; //50 volatile unsigned int hdr_ddr_target_config; volatile unsigned int reserved20; volatile unsigned int reserved21; volatile unsigned int hdr_ddr_target_abr_config; //54 }i3c_tgt_reg_type_t; #endif #if REG8_BIT typedef struct { #if SECONDARY_CONTROLLER_ENABLE //used for secondary controller connection volatile unsigned char reserved[128]; #endif volatile unsigned char bcr; //00 volatile unsigned char dcr; volatile unsigned char dyn_addr; volatile unsigned char event_command_en; volatile unsigned char event_command_dev_config; volatile unsigned char event_command_req; //05 volatile unsigned char hj_ibi_retry; volatile unsigned char max_wr_legth_msb; volatile unsigned char max_wr_legth_lsb; volatile unsigned char max_rd_legth_msb; volatile unsigned char max_rd_legth_lsb; //A volatile unsigned char max_ibi_payload; volatile unsigned char max_wr_data_speed; volatile unsigned char max_rd_data_spped; volatile unsigned char max_rd_turnout_time_msb; volatile unsigned char max_rd_turnout_time; //F volatile unsigned char max_rd_turnout_time_lsb; volatile unsigned char dev_provisioned_id6; volatile unsigned char dev_provisioned_id5; volatile unsigned char dev_provisioned_id4; //13 volatile unsigned char dev_provisioned_id3; volatile unsigned char dev_provisioned_id2; volatile unsigned char dev_provisioned_id1; volatile unsigned char static_addr; //17 volatile unsigned char dev_capabilities_byte1; volatile unsigned char dev_capabilities_byte2; volatile unsigned char dev_capabilities_byte3; volatile unsigned char reserved1; volatile unsigned char osc_inacc; volatile unsigned char reserved2; volatile unsigned char reserved3; volatile unsigned char reserved4; volatile unsigned char rx_fifo; //20 volatile unsigned char reserved5; volatile unsigned char tx_fifo; //22 volatile unsigned char reserved6; volatile unsigned char reserved7; volatile unsigned char reserved8; volatile unsigned char reserved9; volatile unsigned char reserved10; volatile unsigned char soft_reset; volatile unsigned char target_response; //29 volatile unsigned char get_status_msb; volatile unsigned char get_status_lsb; volatile unsigned char bus_activity_state; volatile unsigned char tgt_reaction_action_1; volatile unsigned char tgt_reaction_action_2; volatile unsigned char tgt_reaction_action_3; //2F volatile unsigned char interrupt_1; volatile unsigned char interrupt_1_en; //31 volatile unsigned char intrerrupt_1_set; volatile unsigned char interrupt_2; volatile unsigned char interrupt_2_en; //34 volatile unsigned char interrupt_2_set; //35 volatile unsigned char interrupt_3; //36 volatile unsigned char interrupt_3_en; volatile unsigned char interrupt_3_set; volatile unsigned char interrupt_4; //39 volatile unsigned char interrupt_4_en; volatile unsigned char interrupt_4_set; volatile unsigned char interrupt_5; //3C volatile unsigned char interrupt_5_en; volatile unsigned char interrupt_5_set; //3E volatile unsigned char reserved11; volatile unsigned char deftgts_count; //40 volatile unsigned char deftgtsrxfifo_start; volatile unsigned char deftgtsrxfifo_count; volatile unsigned char controller_role_handoff; volatile unsigned char getmxds_con_cap; volatile unsigned char getmxds_con_cap_lsb; //45 volatile unsigned char getmxds_con_cap1; //46 volatile unsigned char getmxds_con_cap2; volatile unsigned char reserved12; volatile unsigned char reserved13; volatile unsigned char reserved14; volatile unsigned char reserved15; //4A volatile unsigned char reserved16; volatile unsigned char reserved17; volatile unsigned char reserved18; volatile unsigned char reserved19; volatile unsigned char bus_mode; //50 volatile unsigned char hdr_ddr_target_config; volatile unsigned char reserved20; volatile unsigned char reserved21; volatile unsigned char hdr_ddr_target_abr_config; //54 }i3c_tgt_reg_type_t; #endif struct i3c_target_handle_t{ unsigned int base_addr; unsigned int len; unsigned int *buf; unsigned int max_retry; unsigned int mdb; unsigned int *ibi_optional_payload; unsigned int ibi_optional_payload_len; }; /* *Function declaration */ unsigned int i3c_target_init(struct i3c_target_handle_t *handle); unsigned int i3c_target_private_write(struct i3c_target_handle_t *handle ); unsigned int i2c_target_write(struct i3c_target_handle_t *handle); unsigned int i3c_target_private_read(struct i3c_target_handle_t *handle); unsigned int i2c_target_read(struct i3c_target_handle_t *handle); unsigned int i3c_target_hj_req(struct i3c_target_handle_t *handle); unsigned int i3c_target_ibi_req(struct i3c_target_handle_t *handle); unsigned int i3c_target_cntrl_role_handoff(struct i3c_target_handle_t *handle); unsigned int i3c_target_hdrddr_write(struct i3c_target_handle_t *handle); unsigned int i3c_target_hdrddr_read(struct i3c_target_handle_t *handle); unsigned int i3c_target_fifo_loopback_enable(struct i3c_target_handle_t *handle); unsigned int i3c_target_daa_wait(struct i3c_target_handle_t *handle); unsigned int i3c_target_static_addr_wait(struct i3c_target_handle_t *handle); #endif /* i3c_target_H_ */