#include"i3c_slave.h"
#include"reg_access.h"



int32_t i3c_slave_init(struct i3c_slave_instance *this_i3cs,uint32_t addr,uint8_t bcr,uint8_t dcr,uint64_t pid,uint8_t dyn_addr,uint8_t mode)
{
	if(NULL == this_i3cs)
	{
		return 1;
	}

	this_i3cs->base_addr=addr;
	this_i3cs->bcr=bcr;
	this_i3cs->dcr=dcr;
	this_i3cs->init_dyn_addr=dyn_addr;
	this_i3cs->trans_mode=mode;
	this_i3cs->pid=pid;

	reg_8b_write(this_i3cs->base_addr ,bcr);

	reg_8b_write(this_i3cs->base_addr| LMMI_INT_STATUS_EN ,0xff);//enable all ints
	return 0;
}

int32_t i3c_slave_read_data(struct i3c_slave_instance *this_i3cs,uint8_t *rx_buf,int32_t rx_length)
{

	if(NULL == this_i3cs)
	{
		return 1;
	}

	for(int i=0;i<rx_length;i++)
	{
		reg_8b_read(this_i3cs->base_addr| I3C_SLAVE_TRANS_FIFO ,&rx_buf[i]);
	}
	return 0;
}

int32_t i3c_slave_send_data(struct i3c_slave_instance *this_i3cs,uint8_t *tx_buf,int32_t tx_length)
{

	if(NULL == this_i3cs)
	{
		return 1;
	}

	for(int i=0;i<tx_length;i++)
	{
		reg_8b_write(this_i3cs->base_addr| I3C_SLAVE_TRANS_FIFO ,tx_buf[i]);
	}
	return 0;
}

int32_t i3c_slave_isr(struct i3c_slave_instance *this_i3cs)
{
	static uint8_t count=0;
	uint8_t status;
	uint8_t sdr_status;
	uint8_t int_status;
	uint8_t fifo_status;

	if(NULL == this_i3cs)
	{
		return 1;
	}


	reg_8b_read(this_i3cs->base_addr | FIFO_STATE,&fifo_status);

	reg_8b_read(this_i3cs->base_addr | LMMI_INT_STATUS,&int_status);

	reg_8b_read(this_i3cs->base_addr | I3C_SLAVE_SDR_STATUS1,&sdr_status);
	if(sdr_status)
		return -1;


	while(int_status & RX_FIFO_NOT_EMPT)
	{

		reg_8b_read(this_i3cs->base_addr | I3C_SLAVE_RECEIVE_FIFO,&this_i3cs->rx_buf[count++]);
		reg_8b_read(this_i3cs->base_addr | FIFO_STATE,&fifo_status);

		if((fifo_status & RFIFO_EMPT)==0)
		{
			reg_8b_write(this_i3cs->base_addr| LMMI_INT_STATUS ,RX_FIFO_NOT_EMPT);
			return 0;
		}

	}

	return 0;
}