/* ================================================================== >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< ------------------------------------------------------------------ Copyright (c) 2006-2018 by Lattice Semiconductor Corporation ALL RIGHTS RESERVED ------------------------------------------------------------------ IMPORTANT: THIS FILE IS AUTO-GENERATED BY LATTICE RADIANT Software. Permission: Lattice grants permission to use this code pursuant to the terms of the Lattice Corporation Open Source License Agreement. Disclaimer: Lattice provides no warranty regarding the use or functionality of this code. It is the user's responsibility to verify the user Software design for consistency and functionality through the use of formal Software validation methods. ------------------------------------------------------------------ Lattice Semiconductor Corporation 111 SW Fifth Avenue, Suite 700 Portland, OR 97204 U.S.A Email: techsupport@latticesemi.com Web: http://www.latticesemi.com/Home/Support/SubmitSupportTicket.aspx ================================================================== */ #ifndef I3C_MASTER_H #define I3C_MASTER_H #include #include #include "ccc.h" #include typedef enum { I2C_LEGACY = 0, /**< Communicate with an I2C device on I3C bus. */ I3C_SDR = 1, /**< Communicate with a slave supporting I3C Standard Data Rate. */ I3C_HDR_DDR = 2, /**< Communicate with a slave supporting I3C HDR Dual Data Rate. */ I3C_CCC = 3, /**< Common Command Code transfers. */ I3C_IBI_READ = 4 /**< Read IBI payload from slaves that support it. */ } i3c_mode; #define BIT(nr) (1 << (nr)) #define MAX_DEVS 32 #define I2C_STANDARD_MODE_FREQ_KHZ 100 /**< I2C stadard speed 100 KHz. */ #define I2C_FAST_MODE_FREQ_KHZ 400 /**< I2C fast mode speed 400 KHz. */ #define I2C_FAST_MODE_PLUS_FREQ_KHZ 1000 /**< I2C fast mode plus speed 1 MHz. */ #define I3C_I2C_ENUMERATE_MODE_FREQ_KHZ 370 /**< I3C enumeration speed 370 KHz. */ #define I3C_SDR_DATA_RATE_12500_KHZ 12500 /**< I3C SDR speed 12.5 MHz. */ //command register value #define CCC_IN_FRAME 0x01 #define REPEATED_START_IN_FRAME 0x02 #define STOP_IN_FRAME 0X04 #define WRDATA_IN_FRAME 0X08 #define RDDATA_IN_FRAME 0X10 #define I2C_COMMAND 0X20 #define HDR_CMD_IN_FRAME 0X40 #define BROADCAST_CMD 0X80 //ccc #define ENTDAA 0x07 #define ENTHDR 0x20 struct i3c_cmd { uint32_t cmd_lo; uint32_t cmd_hi; uint16_t tx_len; const void *tx_buf; uint16_t rx_len; void *rx_buf; uint8_t error; }; struct i3c_master_instance { uint32_t base_addr; struct i3c_cmd cmd; uint16_t devs_nums; uint16_t datstartaddr; uint8_t trans_mode; uint32_t status; uint8_t tx_buf[8]; uint8_t rx_buf[8]; uint8_t addrs[MAX_DEVS]; }; struct i3c_msg{ uint8_t *buf; int32_t len; uint8_t addr; uint8_t flag; }; /** * struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot * @dev: the I3C device that has generated this IBI * @len: length of the payload associated to this IBI * @data: payload buffer */ struct i3c_ibi_slot { struct i3c_dev_desc *dev; uint32_t len; void *data; }; /** * struct i3c_device_ibi_info - IBI information attached to a specific device * @all_ibis_handled: used to be informed when no more IBIs are waiting to be * processed. Used by i3c_device_disable_ibi() to wait for * all IBIs to be dequeued * @pending_ibis: count the number of pending IBIs. Each pending IBI has its * work element queued to the controller workqueue * @max_payload_len: maximum payload length for an IBI coming from this device. * this value is specified when calling * i3c_device_request_ibi() and should not change at run * time. All messages IBIs exceeding this limit should be * rejected by the master * @num_slots: number of IBI slots reserved for this device * @enabled: reflect the IBI status */ struct i3c_device_ibi_info { volatile int pending_ibis; uint32_t max_payload_len; uint32_t num_slots; uint32_t enabled; }; /** * struct i3c_dev_boardinfo - I3C device board information * @init_dyn_addr: initial dynamic address requested by the FW. * @static_addr: static address the I3C device listen on before it's been * assigned a dynamic address by the master. * @pid: I3C Provisional ID exposed by the device. This is a unique identifier * that may be used when the device * does not have a static address */ struct i3c_dev_boardinfo { uint8_t init_dyn_addr; uint8_t static_addr; uint8_t bcr; uint8_t dcr; uint64_t pid; }; #define I3C_BUS_MAX_DEVS 11 #define I3C_BUS_MAX_I3C_SCL_RATE 50000000 /*REGS*/ #define I3C_MASTER_CLKPERIOD 0x04 #define clk_period_in_20ns 0x14 //50MHZ #define clk_period_in_8ns 0x08 #define clk_period_in_13ns 0x0d #define clk_period_in_10ns 0x10 #define I3C_MASTER_ADDR_REG 0x10*4 #define I3C_MASTER_START_REG 0x11*4 #define I3C_MASTER_NUM_SLAVES 0x13*4 #define I3C_MASTER_INTR_STA 0x20*4 #define I3C_INT_SLAVE_NACK 0x80 #define I3C_INT_COMMAND_DONE 0x40 #define I3C_INT_SMR 0x20 #define I3C_INT_IBI 0x10 #define I3C_INT_HJ 0x08 #define I3C_INT_W_FIFO_FULL 0x04 #define I3C_INT_R_FIFO_n_EMPTY 0x02 #define I3C_MASTER_INTR_SET 0x21*4 #define I3C_MASTER_INTR_ENABLE 0x22*4 #define I3C_MASTER_HDR_SLAVE_INTR_STA 0x23*4 #define I3C_MASTER_HDR_INTR_ENABLE 0x24*4 #define I3C_MASTER_BUS_CONDITION 0x25*4 #define I3C_MASTER_SETUP_TIME 0x26*4 #define I3C_MASTER_DELAY_TIME 0x27*4 #define I3C_MASTER_WRITE_FIFO 0x30*4 #define I3C_MASTER_READ_FIFO 0x40*4 int32_t i3c_master_init(struct i3c_master_instance *this_i3cm,uint32_t addr,uint8_t mode,uint8_t clk,uint8_t slave_nums); int32_t i3c_master_daa(struct i3c_master_instance *this_i3cm,struct i3c_dev_boardinfo *m,uint8_t *dyn_address,int32_t device_count); int32_t i3c_master_getaccr(struct i3c_master_instance *this_i3cm, uint8_t dyn_addr); int32_t i3c_master_private_i3c_write(struct i3c_master_instance *this_i3cm,uint8_t *wr_buf,uint8_t wr_length,uint8_t rd_length,uint8_t slave_dyn_addr); int32_t i3c_master_private_i2c_write(struct i3c_master_instance *this_i3cm,uint8_t *wr_buf,uint8_t wr_length,uint8_t rd_length,uint8_t slave_dyn_addr); int32_t i3c_master_private_i3c_read(struct i3c_master_instance *this_i3cm,uint8_t *rd_buf,uint8_t wr_length,uint8_t rd_length,uint8_t slave_dyn_addr); int32_t i3c_master_private_i2c_read(struct i3c_master_instance *this_i3cm,uint8_t *rd_buf,uint8_t wr_length,uint8_t rd_length,uint8_t slave_dyn_addr); int32_t i3c_master_send_ccc_cmd(struct i3c_master_instance *this_i3cm,struct i3c_ccc_cmd *ccc); /* void i3c_master_wr_tx_fifo(struct i3c_master_instance *this_i3cm,const uint8_t *bytes, int32_t nbytes); void i3c_master_read_rx_fifo(struct i3c_master_instance *this_i3cm,uint8_t *bytes, int32_t nbytes); int32_t i3c_request_ibi(void); int32_t i3c_free_ibi(void); */ #endif /* I3C_MASTER_H */