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IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ #ifndef I3C_CONTROLLER_H #define I3C_CONTROLLER_H #include #include #include #include #include "ccc.h" #define I3C_CONTROLLER_DRV_VER "v1.0.1" #define I3C_BROADCAST_ADDR 0x7e #define I3C_SLAVE_NUMS 1 #define I3C_SLAVE_ADDRESS 0x09 #define ENABLE_DAA_UID #define I3C_INT0_DEFAULT_STATUS 0xc7 #define MASK_CLEAR 0xFF #define I3C_SYS_CLK_DIV 1 #define I3C_OD_TIMER 6 #define I3C_I2C_CLK_DIV 0x30 #define I3C_SDA_WPU_N 1 //Set And Clear #define SET 0x01 #define CLEAR 0x00 #define ALL_BITS_EN 0xff #define MAX_DEVS 32 #define MAX_CLK_VALUE 15 #define I2C_STANDARD_MODE_FREQ_KHZ 100 /**< I2C stadard speed 100 KHz. */ #define I2C_FAST_MODE_FREQ_KHZ 400 /**< I2C fast mode speed 400 KHz. */ #define I2C_FAST_MODE_PLUS_FREQ_KHZ 1000 /**< I2C fast mode plus speed 1 MHz. */ #define I3C_I2C_ENUMERATE_MODE_FREQ_KHZ 370 /**< I3C enumeration speed 370 KHz. */ #define I3C_SDR_DATA_RATE_12500_KHZ 12500 /**< I3C SDR speed 12.5 MHz. */ //command register value #define CCC_IN_FRAME 0x01 #define REPEATED_START_IN_FRAME 0x02 #define STOP_IN_FRAME 0x04 #define START_OF_CCC 0x08 #define I2C_COMMAND 0x10 #define WAIT_NEXT_PACKET 0x20 //Broadcast CCC commands #define ENEC_B 0x00 //Broadcast R #define DISEC_B 0x01 //Broadcast R #define ENTAS0_B 0x02 //Broadcast C #define ENTAS1_B 0x03 //Broadcast O #define ENTAS2_B 0x04 //Broadcast O #define ENTAS3_B 0x05 //Broadcast O #define RSTDAA 0x06 //Broadcast R #define ENTDAA 0x07 //Broadcast R #define DEFTGTS 0x08 //Broadcast C #define SETMWL_B 0x09 //Broadcast R #define SETMRL_B 0x0A //Broadcast R #define ENDXFER_B 0x12 //Broadcast C #define ENTHDR0 0x20 //Broadcast C #define SETXTIME 0x28 //Broadcast C #define SETAASA 0x29 //Broadcast O #define RSTACT 0x2A //Broadcast R //Direct CCC commands #define ENEC_D 0x80 //Direct R #define DISEC_D 0x81 //Direct R #define ENTAS0_D 0x82 //Direct C #define ENTAS1_D 0x83 //Direct O #define ENTAS2_D 0x84 //Direct O #define ENTAS3_D 0x85 //Direct O #define SETDASA 0x87 //Direct O #define SETNEWDA 0x88 //Direct C #define SETMWL_D 0x89 //Direct R #define SETMRL_D 0x8A //Direct R #define GETMWL 0x8B //Direct R #define GETMRL 0x8C //Direct R #define GETPID 0x8D //Direct C #define GETBCR 0x8E //Direct C #define GETDCR 0x8F //Direct C #define GETSTATUS 0x90 //Direct R #define GETACCCR 0x91 //Direct C #define ENDXFER_D 0x92 //Direct C /*REGS*/ #define I3C_MASTER_CLKPERIOD 0x01*4 #define I3C_MASTER_CFG0 0x02*4 #define I3C_MASTER_START_REG 0x11*4 #define I3C_MASTER_DA_ACK_REG 0x1C*4 #define I3C_MASTER_INTR_STA 0x20*4 #define I3C_MASTER_INTR_STA1 0x24*4 //int status0 #define I3C_INT0_SLAVE_NACK 0x80 #define I3C_INT0_COMMAND_DONE 0x40 #define I3C_INT0_RCVD_IBI 0x20 #define I3C_INT0_RCVD_SEC_IBI 0x10 #define I3C_INT0_RCVD_HOT_JOIN 0x08 #define I3C_INT0_W_FIFO_FULL 0x04 #define I3C_INT0_R_FIFO_n_EMPTY 0x02 #define I3C_INT0_RD_CMD_DONE 0x01 //int status1 #define I3C_INT1_RESERVED 0x80 #define I3C_INT1_WAITTING_IBI_RESP 0x40 #define I3C_INT1_RX_FIFO_FULL 0x20 #define I3C_INT1_CRH_TIMEOUT_EXPIRED 0x10 #define I3C_INT1_GET_ACCCR_DONE 0x08 #define I3C_INT1_IBI_RD_DONE 0x04 #define I3C_INT1_WR_EARLY_TERM 0x02 #define I3C_INT1_RD_EARLY_TERM 0x01 //int enable 0 #define RCVD_IBI_EN 0x10 #define RCVD_HOT_JOIN_EN 0x08 //cfg0 #define IBI_AUTO_RESP 0x20 #define I3C_MASTER_IBI_RD_CNT 0x1D*4 #define I3C_MASTER_IBI_RESP 0x1E*4 #define I3C_MASTER_IBI_ADDR 0x1F*4 #define I3C_MASTER_INTR_SET 0x21*4 #define I3C_MASTER_INTR_ENABLE 0x22*4 #define I3C_MASTER_INTR1_SET 0x25*4 #define I3C_MASTER_WRITE_FIFO 0x30*4 #define I3C_MASTER_READ_FIFO 0x40*4 /*i3c master v3.0 regs*/ #define IGNORE_CMD_DONE 0x10 #define I2C_MODE_ALLOWED 0x08 #define I3C_MODE_ALLOWED 0x20 #define IGNORE_RCVD_NAK 0x04 #define EN_DAA_UID_IN_RXFIFO 0x02 #define I3C_PRIV_RW_NO_7E 0x01 #define I3C_MASTER_OPEN_DRAIN_TIMER 0x03*4 #define I2C_CLK_DIVIDER 0x04*4 #define I3C_MASTER_SOFT_RESET 0x08*4 #define I3C_MASTER_PULL_UP_RESISTOR_DISABLE 0x05*4 #define IP_CSR_RST 0x10 #define IP_CORE_RST 0x08 #define TX_FIFO_RST 0x04 #define RX_FIFO_RST 0x02 #define IP_MAIN_RST 0x01 #define START 0x01 #define RCVD_IBI 0x10 #define ACK_IBI 0x00 #define NACK_IBI 0x01 #define RCVD_HJ 0x08 #define ACK_HJ 0x00 #define NACK_HJ 0x01 struct i3c_master_instance { uint32_t base_addr; uint32_t status; uint16_t devs_nums; uint8_t trans_mode; uint8_t *tx_buf; uint8_t *rx_buf; uint8_t addrs[MAX_DEVS]; }; struct i3c_dev_info { uint8_t init_dyn_addr; uint8_t static_addr; uint8_t bcr; uint8_t dcr; uint64_t pid; }; typedef enum { MCTP_OVER_I3C = 0, MCTP_OVER_I2C, } mctp_path_e; typedef enum { I3C_IDLE = 0, I3C_RECEIVE, I3C_RECEIVE_DONE, I3C_SEND, I3C_SEND_DONE, I3C_TEST, } mctp_i3c_phase_e; uint8_t i3c_master_init(struct i3c_master_instance *this_i3cm,uint32_t addr,uint8_t mode,uint8_t clk,uint8_t slave_nums); uint8_t i3c_master_daa(struct i3c_master_instance *this_i3cm,struct i3c_dev_info *dev,uint8_t *dyn_address,uint32_t device_count,uint8_t slave_addr); uint8_t i3c_master_private_i3c_write(struct i3c_master_instance *this_i3cm, uint8_t *wr_buf, uint8_t wr_length, uint8_t slave_dyn_addr); uint8_t i3c_master_private_i2c_write(struct i3c_master_instance *this_i3cm, uint8_t *wr_buf, uint8_t wr_length, uint8_t slave_dyn_addr); uint8_t i3c_master_private_i3c_read(struct i3c_master_instance *this_i3cm, uint8_t *rd_buf, uint8_t rd_length, uint8_t slave_dyn_addr); uint8_t i3c_master_private_i2c_read(struct i3c_master_instance *this_i3cm, uint8_t *rd_buf, uint8_t rd_length, uint8_t slave_dyn_addr); uint8_t i3c_master_private_i3c_read_handle_early_term(struct i3c_master_instance *this_i3cm, uint8_t *rd_buf, uint8_t expected_rd_length,uint8_t slave_dyn_addr, uint8_t *actual_rd_length); uint8_t i3c_master_private_i3c_write_repeated_start_read_handle_early_term(struct i3c_master_instance *this_i3cm, uint8_t *wr_buf,uint8_t wr_length,uint8_t slave_dyn_addr, uint8_t expected_rd_length, uint8_t *rd_buf, uint8_t *actual_rd_length); uint8_t i3c_master_direct_ccc(struct i3c_master_instance *this_i3cm, uint8_t slave_address, int size_A, uint8_t *buffer_A, int size_B, uint8_t *buffer_B, uint8_t read_write, uint8_t *return_value, int *return_value_size); uint8_t i3c_master_broadcast_ccc(struct i3c_master_instance *this_i3cm, int size, unsigned char *buffer, unsigned char *return_value, int *return_value_size); uint8_t i3c_master_ibi_Init(struct i3c_master_instance *this_i3cm); uint8_t fill_the_I3C_MASTER_WRITE_FIFO(struct i3c_master_instance *this_i3cm, uint32_t size, uint8_t *buffer); #endif /* I3C_CONTROLLER_H */