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IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ #ifndef I3C_CONTROLLER_H_ #define I3C_CONTROLLER_H_ #include /*Driver details*/ #define DRIVER_MAJOR_VERSION 1 #define DRIVER_MINOR_VERSION 0 #define DRIVER_TEST_VERSION 0 //Reg 32-bit and 8-bit #define REG_32_BIT 1 #define REG_8_BIT 0 //Success and Failure #define FAILURE 0 #define SUCCESS 1 //Write and Read #define WRITE 0 #define READ 1 //Address #define RESERVED_ADDRESS 0x7e #define I3C_MODE 1 //Set And Clear #define SET 0x01 #define CLEAR 0x00 #define ALL_BITS_EN 0xff //Shift Values #define READ_LEFT_SHIFT 0x01 #define READ_RIGHT_SHIFT 0X80 #define FIVE_SHIFT 5 #define EIGHT_LEFT_SHIFT 8 #define ZERO 0 //command register value #define CCC_CMD1_WR_RD0 0x01 #define REPEATED_START_IN_FRAME 0x02 #define STOP_IN_FRAME 0X04 #define CCC_COMMAND_WITH_START 0X08 #define I2C_FRAME 0x10 #define WAIT_NEXT_PACKET 0X20 #define HDR_MODE 0X80 //interrupt bits #define EN_DAA_UID_IN_RXFIFO 0x02 #define IGNORE_RCVD_NAK 0x04 #define IGNORE_CMD_DONE 0x10 #define RCVD_SLAVE_NACK 0x80 #define RCVD_CMND_DONE 0x40 #define TX_FIFO_FULL 0X04 #define RX_FIFO_n_EMPTY 0x02 #define RD_CMD_DONE 0x01 #define DDR_IGNORE_CMD_DONE 0x08 #define NO_CRC_AFTER_TERM 0X04 #define EN_WR_EARLY_TERM 0x02 #define EN_WRCMD_ACKNAK_CAP 0X01 #define I2C_MODE_ALLOWED 0x28 #define I3C_MODE_ALLOWED 0x20 #define HDR_RD_CMD_DONE 0x01 #define HDR_SLAVE_NACK 0x80 #define HDR_CMND_DONE 0x40 #define WAITING_IBI_RESP 0x40 #define PULL_UP_RES_DISABLE 0X09 //values #define MAX_ADRR_SIZE 127 #define START 0x01 #define MAX_FIFO_SIZE 256 //Hot-join and IBI #define IBI_AUTO_RESP_LOW 0xdf #define IBI_RD_DONE_EN 0X04 #define IBI_INTRPT_RCVD 0X10 #define HOT_JOIN_INTRPT_RCVD 0X08 #define IBI_AUTO_RESP 0x20 //Controller handoff #define SEC_CTRRL_INTRPT_RCVD 0X20 #define GET_ACCR_DONE 0x08 #define GET_ACCR_RESULT 0x04 #define CRH_TIMEOUT_VALUE 0x009C4 #define CRH_TIMEOUT_VALUE_REG17 0x000ff #define CRH_TIMEOUT_VALUE_REG18 0x0ff00 #define CRH_TIMEOUT_VALUE_REG19 0xf0000 //Broadcast CCC commands #define ENEC_B 0x00 //Broadcast R #define DISEC_B 0x01 //Broadcast R #define ENTAS0_B 0x02 //Broadcast C #define ENTAS1_B 0x03 //Broadcast O #define ENTAS2_B 0x04 //Broadcast O #define ENTAS3_B 0x05 //Broadcast O #define RSTDAA 0x06 //Broadcast R #define ENTDAA 0x07 //Broadcast R #define DEFTGTS 0x08 //Broadcast C #define SETMWL_B 0x09 //Broadcast R #define SETMRL_B 0x0A //Broadcast R #define ENDXFER_B 0x12 //Broadcast C #define ENTHDR0 0x20 //Broadcast C #define SETXTIME 0x28 //Broadcast C #define SETAASA 0x29 //Broadcast O #define RSTACT 0x2A //Broadcast R //Direct CCC commands #define ENEC_D 0x80 //Direct R #define DISEC_D 0x81 //Direct R #define ENTAS0_D 0x82 //Direct C #define ENTAS1_D 0x83 //Direct O #define ENTAS2_D 0x84 //Direct O #define ENTAS3_D 0x85 //Direct O #define SETDASA 0x87 //Direct O #define SETNEWDA 0x88 //Direct C #define SETMWL_D 0x89 //Direct R #define SETMRL_D 0x8A //Direct R #define GETMWL 0x8B //Direct R #define GETMRL 0x8C //Direct R #define GETPID 0x8D //Direct C #define GETBCR 0x8E //Direct C #define GETDCR 0x8F //Direct C #define GETSTATUS 0x90 //Direct R #define GETACCCR 0x91 //Direct C #define ENDXFER_D 0x92 //Direct C #if REG_32_BIT typedef struct { volatile unsigned int reserved0; //0x00 volatile unsigned int i3c_controller_clock_divider; //0x01 volatile unsigned int i3c_controller_config0; volatile unsigned int i3c_controller_open_drain; volatile unsigned int i3c_controller_i2c_clock_divider; volatile unsigned int pull_up_resistor_disable; //0x05 volatile unsigned int hdr_ddr_config0; volatile unsigned int soft_reset_register; volatile unsigned int reserved1[9]; //reserved 0x08 to 0x10 volatile unsigned int i3c_controller_start_reg; volatile unsigned int reserved2[3]; //reserved 0x12 to 0x14 volatile unsigned int secondary_contr_status; volatile unsigned int set_device_role; volatile unsigned int secondary_contr_timeout_17 ; //0x17 volatile unsigned int secondary_contr_timeout_18 ; //0x18 volatile unsigned int secondary_contr_timeout_19 ; //0x19 volatile unsigned int reserved3[2]; //reserved 0x1a to 0x1b volatile unsigned int i3c_controller_da_ack_reg; volatile unsigned int ibi_read_count_register; volatile unsigned int ibi_response_register; volatile unsigned int ibi_address_register; //0x1f volatile unsigned int i3c_controller_intrpt_status0; volatile unsigned int i3c_controller_intrpt_set0; volatile unsigned int i3c_controller_intrpt_enable0; volatile unsigned int reserved4; //reserved 0x23 volatile unsigned int i3c_controller_intrpt_status1; volatile unsigned int i3c_controller_intrpt_set1; volatile unsigned int i3c_controller_intrpt_enable1; volatile unsigned int reserved5; //reserved 0x27 volatile unsigned int bus_cond_debug; volatile unsigned int last_nack_addr; volatile unsigned int last_ack_addr; volatile unsigned int reserved6; //reserved 0x2b volatile unsigned int i3c_controller_intrpt_status2; volatile unsigned int i3c_controller_intrpt_set2; volatile unsigned int i3c_controller_intrpt_enable2; volatile unsigned int reserved7; //reserved 0x2f volatile unsigned int i3c_controller_tx_fifo; // 0x30 volatile unsigned int reserved[15]; //reserved 0x31 to 0x3f volatile unsigned int i3c_controller_rx_fifo; }i3c_cntler_reg_t; #endif #if REG_8_BIT typedef struct { volatile unsigned char reserved0; //0x00 volatile unsigned char i3c_controller_clock_divider; //0x01 volatile unsigned char i3c_controller_config0; volatile unsigned char i3c_controller_open_drain; volatile unsigned char i3c_controller_i2c_clock_divider; volatile unsigned char pull_up_resistor_disable; //0x05 volatile unsigned char hdr_ddr_config0; volatile unsigned char soft_reset_register; volatile unsigned char reserved1[9]; //reserved 0x08 to 0x10 volatile unsigned char i3c_controller_start_reg; volatile unsigned char reserved2[3]; //reserved 0x12 to 0x14 volatile unsigned char secondary_contr_status; volatile unsigned char set_device_role; volatile unsigned char secondary_contr_timeout_17 ; //0x17 volatile unsigned char secondary_contr_timeout_18 ; //0x18 volatile unsigned char secondary_contr_timeout_19 ; //0x19 volatile unsigned char reserved3[2]; //reserved 0x1a to 0x1b volatile unsigned char i3c_controller_da_ack_reg; volatile unsigned char ibi_read_count_register; volatile unsigned char ibi_response_register; volatile unsigned char ibi_address_register; //0x1f volatile unsigned char i3c_controller_intrpt_status0; volatile unsigned char i3c_controller_intrpt_set0; volatile unsigned char i3c_controller_intrpt_enable0; volatile unsigned char reserved4; //reserved 0x23 volatile unsigned char i3c_controller_intrpt_status1; volatile unsigned char i3c_controller_intrpt_set1; volatile unsigned char i3c_controller_intrpt_enable1; volatile unsigned char reserved5; //reserved 0x27 volatile unsigned char bus_cond_debug; volatile unsigned char last_nack_addr; volatile unsigned char last_ack_addr; volatile unsigned char reserved6; //reserved 0x2b volatile unsigned char i3c_controller_intrpt_status2; volatile unsigned char i3c_controller_intrpt_set2; volatile unsigned char i3c_controller_intrpt_enable2; volatile unsigned char reserved7; //reserved 0x2f volatile unsigned char i3c_controller_tx_fifo; // 0x30 volatile unsigned char reserved[15]; //reserved 0x31 to 0x3f volatile unsigned char i3c_controller_rx_fifo; }i3c_cntler_reg_t; #endif typedef struct { bool mode; unsigned int len; unsigned int *buf; unsigned int scl_clk_divider; unsigned int base_addr; unsigned int target_dyn_addr; unsigned int target_static_addr; unsigned int target_nums; unsigned int direct_ccc_optnal_bytes; unsigned int *direct_ccc_optnal_data_array; unsigned int target2_dyn_addr; unsigned int len2; unsigned int *buf2; unsigned int ibi_read_count; unsigned int *ibi_payload_data; unsigned int user_7bit_code; unsigned int blocking_write; unsigned int target_dyn_addr_multi[]; }i3c_controller_handle_t ; typedef struct { unsigned int init_dyn_addr; unsigned int bcr; unsigned int dcr; unsigned int pid; }i3c_dev_info_t; unsigned int i3c_controller_init(i3c_controller_handle_t *handle); unsigned int i3c_controller_daa_1tgt(i3c_controller_handle_t *handle,i3c_dev_info_t *info); unsigned int i3c_controller_entdaa_multitargets(i3c_controller_handle_t *handle); unsigned int i3c_controller_private_i3c_write(i3c_controller_handle_t *handle ); unsigned int i3c_controller_private_i3c_read(i3c_controller_handle_t *handle ); unsigned int i3c_controller_private_i2c_write(i3c_controller_handle_t *handle ); unsigned int i3c_controller_private_i2c_read(i3c_controller_handle_t *handle ); unsigned int i3c_controller_hdr_ddr_write(i3c_controller_handle_t *handle); unsigned int i3c_controller_hdr_ddr_read(i3c_controller_handle_t *handle); unsigned int i3c_controller_direct_ccc(i3c_controller_handle_t *handle,bool read1_write0) ; unsigned int i3c_controller_broadcast_ccc(i3c_controller_handle_t *handle); unsigned int i3c_controller_Consecutive_private_i3c_write(i3c_controller_handle_t *handle); unsigned int i3c_controller_Consecutive_private_i3c_write_read(i3c_controller_handle_t *handle); unsigned int i3c_controller_Consecutive_private_i2c_write_read(i3c_controller_handle_t *handle ); unsigned int i3c_controller_Consecutive_hdr_ddr_write_read(i3c_controller_handle_t *handle); unsigned int i3c_controller_hj_handling(i3c_controller_handle_t *handle,bool ibi_config); unsigned int i3c_controller_ibi_handling(i3c_controller_handle_t *handle,bool ibi_config ); unsigned int i3c_controller_Contrlr_handoff(i3c_controller_handle_t *handle); unsigned int i3c_controller_hdr_broadcast_ccc(i3c_controller_handle_t *handle); unsigned int i3c_controller_hdr_direct_ccc(i3c_controller_handle_t *handle,bool read1_write0); #endif /* I3C_CONTROLLER_H_ */