/*   ==================================================================
     >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2006-2018 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

    IMPORTANT: THIS FILE IS AUTO-GENERATED BY LATTICE RADIANT Software.

     Permission:

    Lattice grants permission to use this code pursuant to the
    terms of the Lattice Corporation Open Source License Agreement.

     Disclaimer:

    Lattice provides no warranty regarding the use or functionality
    of this code. It is the user's responsibility to verify the
    user Software design for consistency and functionality through
    the use of formal Software validation methods.

     ------------------------------------------------------------------

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     U.S.A

     Email: techsupport@latticesemi.com
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     ================================================================== */

#ifndef I3C_MASTER_H
#define I3C_MASTER_H

#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include "ccc.h"


#define MAX_DEVS							32
#define MAX_CLK_VALUE						15
#define I2C_STANDARD_MODE_FREQ_KHZ          100     /**< I2C stadard speed 100 KHz. */
#define I2C_FAST_MODE_FREQ_KHZ              400     /**< I2C fast mode speed 400 KHz. */
#define I2C_FAST_MODE_PLUS_FREQ_KHZ         1000    /**< I2C fast mode plus speed 1 MHz. */
#define I3C_I2C_ENUMERATE_MODE_FREQ_KHZ     370     /**< I3C enumeration speed 370 KHz. */
#define I3C_SDR_DATA_RATE_12500_KHZ         12500   /**< I3C SDR speed 12.5 MHz. */

//command register value
#define CCC_IN_FRAME        				0x01
#define REPEATED_START_IN_FRAME             0x02
#define STOP_IN_FRAME                       0X04
#define START_OF_CCC						0x08
#define I2C_COMMAND		                    0X10
#define WAIT_NEXT_PACKET                    0X20


/*ccc command*/
#define ENTDAA 0x07
#define ENTHDR 0x20



struct i3c_master_instance {
	uint32_t base_addr;
	uint32_t status;
	uint16_t devs_nums;
	uint8_t  trans_mode;
	uint8_t  *tx_buf;
	uint8_t  *rx_buf;
	uint8_t  addrs[MAX_DEVS];
};


struct i3c_dev_info {
	uint8_t init_dyn_addr;
	uint8_t static_addr;
	uint8_t bcr;
	uint8_t dcr;
	uint64_t pid;

};

/*REGS*/
#define I3C_MASTER_CLKPERIOD 		  	0x01*4
#define I3C_MASTER_CFG0					0x02*4
#define I3C_MASTER_START_REG	    	0x11*4
#define I3C_MASTER_DA_ACK_REG	    	0x1C*4
#define I3C_MASTER_INTR_STA 			0x20*4
#define I3C_INT_SLAVE_NACK				0x80
#define I3C_INT_COMMAND_DONE 			0x40
#define I3C_INT_W_FIFO_FULL 			0x04
#define I3C_INT_R_FIFO_n_EMPTY			0x02
#define I3C_INT_RD_CMD_DONE 			0x01

#define I3C_MASTER_IBI_RD_CNT 			0x1D*4
#define I3C_MASTER_IBI_RESP 			0x1E*4
#define I3C_MASTER_IBI_ADDR 			0x1F*4

#define I3C_MASTER_INTR_SET 			0x21*4
#define I3C_MASTER_INTR_ENABLE 			0x22*4

#define I3C_MASTER_WRITE_FIFO 			0x30*4
#define I3C_MASTER_READ_FIFO 			0x40*4

/*i3c master v3.0 regs*/

#define IGNORE_CMD_DONE			0x10
#define	I2C_MODE_ALLOWED		0x08
#define IGNORE_RCVD_NAK     	0x04
#define	EN_DAA_UID_IN_RXFIFO	0x02
#define I3C_PRIV_RW_NO_7E    	0x01
#define I3C_MASTER_OPEN_DRAIN_TIMER		0x03*4
#define I3C_MASTER_SOFT_RESET			0x08*4
#define IP_CSR_RST				0x10
#define	IP_CORE_RST				0x08
#define TX_FIFO_RST		     	0x04
#define	RX_FIFO_RST				0x02
#define IP_MAIN_RST		    	0x01
#define START					0x01

#define RCVD_IBI				0x10
#define ACK_IBI					0x00
#define NACK_IBI				0x01

#define RCVD_HJ					0x08
#define ACK_HJ					0x00
#define NACK_HJ				0x01

uint8_t i3c_master_init(struct i3c_master_instance *this_i3cm,uint32_t addr,uint8_t mode,uint8_t clk,uint8_t slave_nums);
uint8_t i3c_master_daa(struct i3c_master_instance *this_i3cm,struct i3c_dev_info *dev,uint8_t *dyn_address,uint32_t device_count,uint8_t slave_addr);
uint8_t i3c_master_private_i3c_write(struct i3c_master_instance *this_i3cm,uint8_t *wr_buf,uint8_t wr_length,uint8_t slave_dyn_addr);
uint8_t i3c_master_private_i2c_write(struct i3c_master_instance *this_i3cm,uint8_t *wr_buf,uint8_t wr_length,uint8_t slave_dyn_addr);
uint8_t i3c_master_private_i3c_read(struct i3c_master_instance *this_i3cm,uint8_t *rd_buf,uint8_t rd_length,uint8_t slave_dyn_addr);
uint8_t i3c_master_private_i2c_read(struct i3c_master_instance *this_i3cm,uint8_t *rd_buf,uint8_t rd_length,uint8_t slave_dyn_addr);

#endif /* I3C_MASTER_H */