I2C Target

Description

The I2C Target IP provides a bridge between LMMI/APB interface and standard external I2C bus interface. It supports out-of-band interrupt and configurable transmit and receive FIFO to minimize intervention by the host. The following I2C features are supported:

Supports 7-bit and 10-bit Addressing Mode
Supports the following bus speeds: Standard-mode, Fast-mode, Fast-mode Plus
Supports Clock stretching
Integrated Pull-up
Integrated Glitch filter

Devices Supported

LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, UT24C40, UT24CP100, LAV-AT-500E

References

User Guide

Revision History

2.0.0	Updated terminologies to use Controller and Target
1.4.1	Added driver version number, more comments, and removed magic numbers.
1.4.0	Added Avant support.
1.3.0	Modified metadata.xml to change minimum value of Tx/Rx_FIFO_Almost_Full/Empty_Flag to 1.
1.2.0	Added LFMXO5 support.
1.1.0	Added LFCPNX support.
1.0.3	Reduced read latency by from 2 clock cycle to 1 clock cycle. Added Certus-NX support.
1.0.2	Updated for Radiant 2.0 Service Pack 1.
1.0.1	Initial release.
1.0.0	Preliminary release.