I2C Master

Description

The I2C Master IP Core provides a bridge between LMMI/APB interface and standard external I2C bus interface. It supports out-of-band interrupt and configurable transmit/receive FIFO size to minimize intervention by the host. The following I2C features are supported:

• Supports 7-bit and 10-bit Addressing Mode
• Supports the following bus speeds: Standard-mode, Fast-mode, Fast-mode Plus
• Supports Clock stretching
• Integrated Pull-up
• Integrated Glitch filter
• Arbitration lost detection in multi-master system

Devices Supported

LIFCL

References

• User Guide

Revision History