The Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Transmitterr IP converts pixel data into a standard OpenLDI serial video interface domain. The input interface for the design consists of the RGB control signals, pixel clock, and up to two pixel data per pixel clock. Output interface consists of a data bus, vertical and horizontal sync flags, a data enable and a clock in OpenLDI (LVDS7:1) interface format and optional debug signal/s.
LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70
| 1.3.1 | Updated Avant primitives for Radiant 2023.2 compatibility. Fixed design and testbench issue related to "JEIDA" format pixel mapping. |
| 1.3.0 | Added LFD2NX-17, LIFCL and LAV-AT support. Added Propel support. Added AXI4 Stream Interface. Testbench enhancement for AXI4-Stream configuration. |
| 1.2.0 | Added LFMXO5-25 support. |
| 1.1.0 |
Added support for JEIDA/VESA mode. Added CertusPro-NX support. |
| 1.0.1 | Testbench enhancement. | 1.0.0 | Initial release. |