The Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Transmitterr IP converts
pixel data into a standard OpenLDI serial video interface domain.
The input interface for the design consists of the RGB control signals,
pixel clock, and up to two pixel data per pixel clock. Output interface
consists of a data bus, vertical and horizontal sync flags, a data enable
and a clock in OpenLDI (LVDS7:1) interface format and optional debug
signal/s.
LIFCL-40, LIFCL-17, LFD2NX-40, LFCPNX-100
| 1.1.0 |
Added support for JEIDA/VESA mode. Added CertusPro-NX support. |
| 1.0.1 | Testbench enhancement. | 1.0.0 | Initial release. |