eSPI Secondary

Description

The Enhanced Serial Peripheral Interface (eSPI) Secondary IP Core is a synchronous serial interface compatible with SPI. The IP is compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0. The following eSPI features are supported:

Supports Single, Dual and Quad modes
Supports Slave triggered transaction
Supports the following channels

Peripheral
Virtual Wires
OOB Message (Tunneled SMBus)
Run-time Flash Access

Supports CRC checking
Supports AHB-Lite or APB

Devices Supported

MachXO3D

MachXO5-NX

MachXO3D

Mach-NX

Revision History

2.0.0	Added Peripheral, OOB Message and Flash Access. Added GPIO Expander Virtual Wire Interface
1.0.2	Added basic testcase functionality (put_vwire command)
1.0.1	Added support for VW index 128-255.
1.0.0	Initial release.