The Lattice Semiconductor D-PHY Tx IP converts 64-bit data to either DSI or CSI-2 data
for Lattice Semiconductor Crosslink-NX, Certus and CertusPro-NX device families.
The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for use in applications
that require a D-PHY transmitter in the FPGA logic.
LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100, LFMXO5-25
1.7.2 |
Added checking of device, package and speed grade to determine the maximum line rate. |
1.7.1 |
Updated the testbench to match the IPUG and RTL AXI-4 stream mapping of wordcount and virtual channel ID. |
1.7.0 |
Added LFMXO5 support. Cleaned up data width warnings. Updated timing constraints. |
1.6.0 |
revert synchronization of reset_n_i to byteclock domain (added in v1.5). Fixed VCS compilation error. Fixed AXI-4 mapping of packet fields. |
1.5.0 |
Fixed 1.2V offset on the clock N-channel when using the Soft PHY implementation. Synchronized reset_n_i in byteclock domain. |
1.4.0 |
Fixed Skew Calibration timing-related entries in GUI. |
1.3.0 |
Fixed counter bit width reset issue in TX Global Controller. Fixed Skew Calibration timing entries in GUI. Fixed LP RX issue in Soft D-PHY configuration. Fixed rounding error of reference clock in testbench. |
1.2.0 |
Added CertusPro-NX support. |
1.1.5 |
Fix for combinational loop in the skew calibration signals. |
1.1.4 |
Code enhancements to fix timing issues at data rates above 2000 Mbps. Captured updated GPLL module v1.2.2 with DIV_DEL parameter. |
1.1.3 |
DPHY packet enable bug fix. c2d_ready_o behaviour fix - assertion of this signal should wait for tinit_done_o. Initial deskew calibration timing fix. |
1.1.2 |
Added initial deskew calibration for data rates above 1.5 Gbps. Added support for optional periodic skew calibration. Changed the implementation of the DSI FIFO within the Packet Formatter module to EBR. Added the actual data rate and the deviation from the target data rate in the configuration window. |
1.1.1 |
Updated testbench for Radiant 2.2 compatibility. |
1.1.0 |
Added support for ordinal data sequence    - previous versions require input data to be lane interleaved. Testbench supports 3-lane configuration when packet formatter is disabled. Supports CIL-enabled configuration. Code enhancements to remove output glitches. External clock option provided for Hard D-PHY. Option for Soft PHY implementation Added Certus-NX support. |
1.0.1 | Update for SP1. | 1.0.0 | Initial release. |