The Lattice Semiconductor D-PHY Tx IP converts 64-bit data to either DSI or
CSI-2 data for Lattice Semiconductor Crosslink-NX family devices.
The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for use in
applications that require a D-PHY transmitter in the FPGA logic.
LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17
| 1.1.2 |
Added initial deskew calibration for data rates above 1.5 Gbps. Added support for optional periodic skew calibration. Changed the implementation of the DSI FIFO within the Packet Formatter module to EBR. Added the actual data rate and the deviation from the target data rate in the configuration window. |
| 1.1.1 |
Updated testbench for Radiant 2.2 compatibility. |
| 1.1.0 |
Added support for ordinal data sequence (previously, input data must be lane interleaved). Testbench supports 3-lane configuration when packet formatter is disabled. Supports CIL-enabled configuration. Code enhancements to remove output glitches. External clock option provided for Hard D-PHY. Option for Soft PHY implementation Added support for LFD2NX. |
1.0.1 | Update for SP1. | 1.0.0 | Initial release. |