<?xml version="1.0"?>
<lsccip:ip version="1.0"
    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
    xmlns:lsccip="http://www.latticesemi.com/XMLSchema/Radiant/ip"
    xmlns:xi="http://www.w3.org/2001/XInclude">

  <lsccip:general>
    <lsccip:vendor>latticesemi.com</lsccip:vendor>
    <lsccip:library>ip</lsccip:library>
    <lsccip:name>dphy_rx</lsccip:name>
    <lsccip:display_name>CSI-2/DSI D-PHY Receiver</lsccip:display_name>
    <lsccip:version>2.2.0</lsccip:version>
    <lsccip:category>Audio_Video_and_Image_Processing</lsccip:category>
    <lsccip:min_radiant_version>2025.1</lsccip:min_radiant_version>
    <lsccip:min_esi_version>2025.1</lsccip:min_esi_version>
    <lsccip:supported_products>
      <lsccip:supported_family name="LIFCL"></lsccip:supported_family>
      <lsccip:supported_family name="LFD2NX"></lsccip:supported_family>
      <lsccip:supported_family name="LFCPNX"></lsccip:supported_family>
      <lsccip:supported_family name="LFMXO5"></lsccip:supported_family>
      <lsccip:supported_family name="LAV-AT"></lsccip:supported_family>
      <lsccip:supported_family name="LKH-CT"></lsccip:supported_family>
      <lsccip:supported_family name="LKH-MH"></lsccip:supported_family>
      <lsccip:supported_family name="LN2-CT"></lsccip:supported_family>
      <lsccip:supported_family name="LN2-MH"></lsccip:supported_family>
    </lsccip:supported_products>
    <lsccip:supported_platforms>
      <lsccip:supported_platform name="esi"/>
      <lsccip:supported_platform name="radiant"/>
    </lsccip:supported_platforms>  
  </lsccip:general>

  <lsccip:settings>
    <lsccip:setting id                 = "FAMILY"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    default            = "LIFCL"
                    value_expr         = "getFamily(1)"
                    editable           = "False"
                    hidden             = "True"
                    title              = "Device Architecture"
                    group1             = "General"
    />

    <lsccip:setting id                 = "DEVICE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Dev"
                    value_expr         = "runtime_info.device_info.device(1)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "General"
    />

    <lsccip:setting id                 = "PACKAGE"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Pack"
                    value_expr         = "runtime_info.device_info.package(1)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "General"
    />
	
    <lsccip:setting id                 = "SPEED"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Speed"
                    value_expr         = "runtime_info.device_info.speed(1)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "General"
    />

    <lsccip:setting id                 = "OPCON"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Operating Condition"
                    value_expr         = "runtime_info.device_info.operation()"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "General"
    />

    <lsccip:setting id                 = "SIM_MODE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Simulation Mode"
                    default            = "False"
                    editable           = "True"
                    hidden             = "True"
                    description        = "Enables Simulation Mode for IMON Controller of Avant."
                    group1             = "General"
    />

    <lsccip:setting id                 = "DUT_INST_NAME"
                    type               = "verilog_macro"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "path"
                    value_expr         = "get_dut_name()"
                    editable           = "bool(0)"
                    hidden             = "bool(1)"
                    group1             = "General"
    />
	
    <lsccip:setting id                 = "RX_TYPE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "RX Interface Type"
                    options            = "['DSI', ('CSI-2', 'CSI2')]"
                    default            = "CSI2"
                    drc                = "ext_device_chk_drc(DEVICE)"
                    group1             = "Receiver"
                    description        = "D-PHY Rx interface type."
    />

    <lsccip:setting id                 = "DPHY_RX_IP"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "D-PHY RX IP"
                    options            = "[('Hard D-PHY', 'MIXEL'),
                                           ('Soft D-PHY', 'LATTICE')]"
                    value_expr         = "getDPHY_DefValue(FAMILY,DEVICE)"
                    default            = "MIXEL"
                    editable           = "FAMILY == 'LIFCL' and (DEVICE == 'LIFCL-17' or DEVICE == 'LIFCL-40')"
                    drc                = "ext_sim_mode_drc(1)"
                    group1             = "Receiver"
                    description        = "Implementation of the PHY layer of the D-PHY Rx. Only the Crosslink-NX 
                                          device supports Hard D-PHY."
    />

    <lsccip:setting id                 = "DATA_R_WIDTH"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Read Data Width"
                    value_expr         = "0 if (not PARSER) else 64 if
                                               (NUM_RX_LANE * RX_GEAR_INPUT == 64)
                                                else 32"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Receiver"
    />

    <lsccip:setting id                 = "NUM_RX_LANE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Number of RX Lanes"
                    options            = "[1, 2, 3, 4]"
                    default            = "4"
                    group1             = "Receiver"
                    description        = "Number of D-PHY Rx high-speed ports. 3-lane configuration is only available when the Packet Parser is disabled."
    />

    <lsccip:setting id                 = "RX_GEAR_INPUT"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "RX Gear"
                    options            = "[8, 16] if (DPHY_RX_IP == 'MIXEL')
                                              else [8]"
                    drc                = "ext_check_gear(
                                              DPHY_RX_IP, RX_GEAR_INPUT)"
                    default            = "8"
                    group1             = "Receiver"
                    description        = "This is the width of the deserialized data stream per data lane. RX Gear = 16 is available only on D-PHY RX IP = ‘Hard D-PHY’. "
    />

    <lsccip:setting id                 = "RX_GEAR"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "RX Gear (param)"
                    value_expr         = "RX_GEAR_INPUT
                                              if (DPHY_RX_IP == 'MIXEL')
                                              else 8"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Receiver"
    />

    <lsccip:setting id                 = "DESKEW_INPUT"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Deskew Calibration Detection"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "True if (RX_LINE_RATE > 1500) else False"
                    editable           = "not (RX_LINE_RATE > 1500)"
                    group1             = "Receiver"
                    description        = "This entry is available when data rate is less than 1.5 Gbps. This is automatically set to enabled (and grayed out) at data rate over 1.5 Gbps as this feature is required for data rates over 1.5 Gbps."
    />

    <lsccip:setting id                 = "DESKEW_EN"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Deskew Enable"
                    value_expr         = "'ENABLED' if ((DPHY_RX_IP == 'MIXEL') and (RX_LINE_RATE > 1500))
                                              else 'ENABLED' if (DESKEW_INPUT) else 'DISABLED'"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Receiver"
    />

<!--   <lsccip:setting id                 = "RX_LINE_RATE"                                                                                    -->
<!--                   type               = "input"                                                                                           -->
<!--                   conn_mod           = "lscc_dphy_rx"                                                                                    -->
<!--                   value_type         = "float"                                                                                           -->
<!--                   title              = "RX Line Rate (Mbps)"                                                                             -->
<!--                   value_range        = "(160 if (RX_GEAR_INPUT == 16) else 80, 2500 if (DPHY_RX_IP == 'MIXEL' and RX_GEAR_INPUT == 16)   -->
<!--                                             else 1800 if (FAMILY == 'LAV-AT') else 1500)"                                                -->
<!--                   drc                = "ext_check_rx_line_rate(                                                                          -->
<!--                                             DPHY_RX_IP, RX_LINE_RATE,FAMILY,PACKAGE)"                                                    -->
<!--                   default            = "1000"                                                                                            -->
<!--                   description        = "up to 2500 Mbps if using Hard D-PHY at Gear 16"                                                  -->
<!--                   group1             = "Clock"                                                                                           -->
<!--   />                                                                                                                                     -->
   
   <lsccip:setting id                 = "RX_LINE_RATE"
                   type               = "input"
                   conn_mod           = "lscc_dphy_rx"
                   value_type         = "float"
                   title              = "RX Line Rate (Mbps)"
                   value_range        = "(160 if (RX_GEAR_INPUT == 16) else 80, value_expr_line_rate (DPHY_RX_IP,FAMILY,PACKAGE,RX_GEAR,SPEED,OPCON))"
                   drc                = "ext_check_rx_line_rate(DPHY_RX_IP, RX_LINE_RATE,FAMILY,PACKAGE,RX_GEAR,SPEED,OPCON)"
                   default            = "800"
                   description        = "For hard D-PHY, the maximum line rate depends on the gearing. For soft D-PHY, the maximum line rate depends on the device, package and speed grade. Please check the device datasheet for more information. "
                   group1             = "Clock"
   />

    <lsccip:setting id                 = "DPHY_CLK_FREQ"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "float"
                    title              = "      D-PHY Clock Frequency (MHz)"
                    value_expr         = "(RX_LINE_RATE / 2.0)"
                    editable           = "False"
                    description        = "Operating frequency of the PHY layer."
                    group1             = "Clock"
    />

    <lsccip:setting id                 = "BYTECLK_MHZ"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Byte Clock Frequency (MHz) int"
                    value_expr         = "math.floor(RX_LINE_RATE / RX_GEAR_INPUT)"
                    drc                = "ext_show_notes(BYTECLK_MHZ_FLOAT,CIL_BYPASS,DPHY_RX_IP,SYNCCLK_MHZ)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Clock"
    />    
    
    <lsccip:setting id                 = "BYTECLK_MHZ_FLOAT"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "float"
                    title              = "      Byte Clock Frequency (MHz)"
                    value_expr         = "(RX_LINE_RATE / RX_GEAR_INPUT)"
                    editable           = "False"
                    hidden             = "False"
                    description        = "Operating byte clock frequency of the IP."
                    group1             = "Clock"
    />   

    <lsccip:setting id                 = "RX_LP_M_FACTOR"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Multiplier M factor for LP signal"
                    value_expr         = "compute_lp_md(DPHY_CLK_FREQ, 10, 1)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Clock"
    />

    <lsccip:setting id                 = "RX_LP_D_FACTOR"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Divider D factor for LP signal"
                    value_expr         = "compute_lp_md(DPHY_CLK_FREQ, 10, 0)"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Clock"
    />

    
    <lsccip:setting id                 = "RX_CLK_MODE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "D-PHY Clock Mode"
                    options            = "[('Continuous', 'HS_ONLY'),
                                           ('Non-Continuous', 'HS_LP')]"
                    default            = "HS_ONLY"
                    group1             = "Clock"
                    description        = "Determines the clock mode of the PHY layer."
    />
    
    <lsccip:setting id                 = "SYNCCLK_MHZ"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "float"
                    title              = "Sync Clock Frequency (MHz)"
                    value_range        = "(60, 200)"
                    default            = "60"
                    editable           = "DPHY_RX_IP == 'LATTICE' or not CIL_BYPASS"
                    group1             = "Clock"
                    description        = "Operating frequency of the components interfaced with the fabric."
    />
    <lsccip:setting id                 = "HSEL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "PLL High Speed Configuration"
                    value_expr         = "'ENABLED' if (RX_LINE_RATE > 1500)
                                              else 'DISABLED'"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Clock"
    />

    <lsccip:setting id                 = "DYN_DEL_TH"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Threshold for enabling IMON"
                    default            = "1000"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Clock"
                    description        = "Threshold before enabling IMONDELAY in IP (Avant only)."
    />

    <lsccip:setting id                 = "DYN_DEL_EN"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable IMONDELAY (Avant Devices)"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "True if (FAMILY == 'LAV-AT' and RX_LINE_RATE >= DYN_DEL_TH) else False"
                    default            = "False"
                    hidden             = "True"
                    editable           = "True"
                    group1             = "Clock"
                    description        = "Enables dynamic ECLK centering thru IMONDELAY (Avant devices only)."
    />

    <lsccip:setting id                 = "DDRDLL_EN"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable DDRDLL Instance"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "True if (FAMILY == 'LAV-AT' and DYN_DEL_EN) else False"
                    default            = "True"
                    hidden             = "True"
                    editable           = "(FAMILY == 'LAV-AT' and DYN_DEL_EN)"
                    group1             = "Clock"
                    description        = "Enables DDRDLL instance inside the soft IP when IMONDELAY is enabled (Avant devices only)."
    />

    <lsccip:setting id                 = "DDRDLL_SHARE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "      Enable DDRDLL Source Mode"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Clock"
                    description        = "When DDRDLL is instantiated, enabling this option will expose DDRDLL output ports to top-level for clock sharing."
    />

    <lsccip:setting id                 = "DYN_SEQ_ON"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Sequential Alignment (Avant Devices)"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Clock"
                    description        = "Enables sequential alignment of IMON for multi-lane configurations (Avant Devices)."
    />

    <lsccip:setting id                 = "TEST_PATTERN"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "HS-RX Skew Calibration Bypass - To fix Tsu/Thold issue found in silicon: DNG-10731"
                    value_expr         = "'0b10000000001000000000000000000000' if (1500 >= RX_LINE_RATE)
                                              else '0b00000000000000000000000000000000'"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Clock"
    />

    <lsccip:setting id                 = "CIL_BYPASS"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "CIL Bypass"
                    bool_value_mapping = "('CIL_BYPASSED', 'CIL_ENABLED')"
                    value_expr         = "False if DPHY_RX_IP == 'MIXEL' else True"
                    default            = "True"
                    editable           = "DPHY_RX_IP == 'MIXEL'"
                    hidden             = "DPHY_RX_IP == 'LATTICE'"
                    description        = "When using D-PHY RX IP = ‘Hard D-PHY’, this option bypasses the built-in Control Interface Logic (CIL) of the Hard D-PHY. CIL is the hardened block that controls the clock and data lane state transitions. If the CIL is bypassed, soft logic is used."
                    group1             = "Module Architecture"
    />

    <!--  lane aligner only works for soft d-phy for now -->
    <lsccip:setting id                 = "LANE_ALIGN"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Lane Aligner Module"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "True if ((DYN_DEL_EN or (LMMI and DPHY_RX_IP == 'LATTICE')) and NUM_RX_LANE > 1) else False"
                    default            = "False"
                    editable           = "NUM_RX_LANE > 1 and DPHY_RX_IP == 'LATTICE' and not DYN_DEL_EN"
                    group1             = "Module Architecture"
                    description        = "Enables the line alignment feature. This feature is available when D-PHY RX IP = “Soft D-PHY”."
    />
    
    <lsccip:setting id                 = "PARSER"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Packet Parser"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "NUM_RX_LANE != 3"
                    editable           = "NUM_RX_LANE != 3"
                    group1             = "Module Architecture"
                    description        = "Enables or disables the packet parser function. When the packet parser is enabled, the IP reads through the contents of the packet header and converts them into CSI-2 or DSI related bus/signal outputs. When this is disabled, the deserialized data are sent out without analyzing the contents."
    />

    
    <lsccip:setting id                 = "AXI4"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable AXI4-Stream Interface"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    description        = "Enables AXI4-Stream interface on the datapath to the fabric."
                    drc                = "ext_phaseout_warn(1,'Legacy AXI4-Stream Interface')"
                    group1             = "Module Architecture"
    />
    
    <lsccip:setting id                 = "LMMI"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable LMMI Interface"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "True"
                    description        = "Enables bus interface for accessing IP registers."
                    group1             = "Module Architecture"
    />

    <lsccip:setting id                 = "CSRCMD_IMPL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "CSR CDC Implementation"
                    description        = "Specify the relationship of clock in LMMI module.
                                          ASYNC - CDC is done through wr/rd command.
                                          SYNC - CDC is done in shadow registers."
                    options            = "['SYNC', 'ASYNC']"
                    default            = "SYNC"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Module Architecture"
    />
    
    <lsccip:setting id                 = "MISC_ON"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Miscellaneous Status Signals"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "CIL_BYPASS"
                    group1             = "Module Architecture"
                    description        = "Enables or disables the miscellaneous status signals. When enabled, select internal signals such as high-speed termination enables are available to the top level IP wrapper. This may be used for debugging purposes."
    />

    <!--            group1             = "Configuration Ports" -->
    <!--            group2             = "Configurability"     --> 
 
    <!-- CRC_CHECK available in all except for dynamic reconfig of hard DPHY with Soft CIL -->
    <lsccip:setting id                 = "CRC_CHECK_IN"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable CRC Check"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "PARSER and not AXI4 and BACK2BACK == 'OFF'"
                    hidden             = "not PARSER"
                    group1             = "Module Architecture"
                    description        = "When this option is checked, CRC checking function 
                                          is enabled based on CRC Check Mode attribute. The IP 
                                          core computes the CRC for the payload and checks 
                                          against the packet footer CRC. CRC error flag with 
                                          valid is provided as output status signals. If CRC 
                                          checking is not required, you do not need to select this option."
    />

    <lsccip:setting id                 = "CRC_CHECK_MODE"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "      CRC Check Mode"
                    options            = "['Static', 'Dynamic'] if LMMI else ['Static']"
                    value_expr         = "'Dynamic' if (LMMI) else 'Static'"
                    default            = "Static"
                    editable           = "CRC_CHECK_IN and LMMI and not (DPHY_RX_IP == 'MIXEL' and CIL_BYPASS)"
                    hidden             = "not CRC_CHECK_IN"
                    drc                = "ext_crcchk_mode(CRC_CHECK_IN)"
                    group1             = "Module Architecture"
                    description        = "Select Static if you want the CRC checking function to operate only 
                                          based on compile-time IP configuration. This setting is suitable for 
                                          cases where you want to enable CRC checking function but do not plan 
                                          to dynamically reconfigure the lane and/or gear of the IP. Select 
                                          Dynamic if you want the CRC checking function to operate based on the 
                                          dynamically configured lane and/or gear. This setting is suitable for 
                                          cases where you want to enable CRC checking for dynamically reconfigured 
                                          lane and/or gear of the IP."
    />

    <lsccip:setting id                 = "CRC_CHECK"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable CRC Check (Static)"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "CRC_CHECK_IN"
                    default            = "False"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Module Architecture"
                    description        = "When this option is checked, the IP core computes the 
                                          CRC for the payload and checks against the packet footer 
                                          CRC. CRC error flag with valid is provided as output 
                                          status signals. This is only valid for compile-time 
                                          configuration."
    />
									   
    <lsccip:setting id                 = "DYNAMIC_RECONFIG"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "      Enable Lane/Gear Reconfiguration"
                    bool_value_mapping = "('ON', 'OFF')"
                    value_expr         = "True if CRC_CHECK_MODE=='Dynamic' else False"
                    default            = "False"
                    editable           = "False"
                    hidden             = "True"
                    group1             = "Module Architecture"
                    description        = "When this option is checked, the CRC checking function performs 
                                          based on the dynamically configured lane and gear."
    />
    
    <lsccip:setting id                 = "REF_DT_STRING"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Default Video Data Type"
                    options            = "ext_get_data_types(RX_TYPE,LMMI)"
                    default            = "custom"
                    editable           = "PARSER"
                    hidden             = "True"
                    group1             = "Parser Configuration"
    />

    <lsccip:setting id                 = "REF_DT"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "       data type value"
                    value_expr         = "ext_dtstring_to_val(RX_TYPE,REF_DT_STRING)"
                    output_formatter   = "nostr"
                    editable           = "REF_DT_STRING == 'custom' and PARSER"
                    drc                = "ext_check_refdt_format(REF_DT)"
                    hidden             = "True"
                    group1             = "Parser Configuration"
    />

    <lsccip:setting id                 = "VCX_ON"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Enable Extended Virtual Channel ID"
                    options            = "['ON', 'OFF', 'DYNAMIC']"
                    default            = "OFF"
                    editable           = "RX_TYPE == 'CSI2' and PARSER"
                    hidden             = "True"
                    group1             = "Parser Configuration"
    />
    
    <!-- CRC_CHECK is only available in hard CIL in lscc_dphy_rx_wrap_cil -->
    <!--lsccip:setting id                 = "CRC_CHECK"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Check for CRC Error"
                    description        =  "CRC checking is only available for CSI-2 on Hard D-PHY with hardened CIL only"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "RX_TYPE == 'CSI2' and PARSER"
                    hidden             = "RX_TYPE == 'DSI' or not PARSER or DPHY_RX_IP == 'LATTICE' or CIL_BYPASS"
                    group1             = "Parser Configuration"
    /-->
    <!-- DSI back to back HS transfer. uses old capture_ctrl (no ecc and crc support. no dynamic reconfig) -->
    <lsccip:setting id                 = "BACK2BACK"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "DSI Back-to-Back HS Packets"
                    description        = "Select 'OFF' when there are low power states between packet transfers. Select 'ON' if 2 or more DSI packets, including Null and Blanking, are transmitted within a single HS transmission. When Back-to-Back packets are received, no ECC or CRC check is done and dynamic reconfiguration is not supported."
                    options            = "['ON', 'OFF']"
                    value_expr         = "'OFF'"
                    default            = "OFF"
                    editable           = "RX_TYPE == 'DSI' and PARSER"
                    hidden             = "RX_TYPE == 'CSI2'"
                    group1             = "Parser Configuration"
    />
    
    <!-- hidden if (DSI && BACKtoBACK) or not PARSER -->
    <lsccip:setting id                 = "DROP_NULL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Drop Null and Blanking Packets"
                    description        = "NULL and BLANKING header and payload are ignored and not transmitted out. for DSI with back-to-back packets, Null and Blanking payload are still transmitted, but the signal lp_av_en_o is deasserted"
                    options            = "['ON', 'OFF', 'DYNAMIC']"
                    default            = "OFF"
                    editable           = "PARSER and not BACK2BACK == 'ON'"
                    hidden             = "True"
                    group1             = "Parser Configuration"
    />

    
    <!-- HS-RX Skew Calibration Bypass - To fix low Tsu/Thold margin found in silicon: DNG-10731 -->    
    <!-- <lsccip:setting id                 = "TEST_PATTERN"                                                       -->
    <!--                type               = "param"                                                               -->
    <!--                conn_mod           = "lscc_dphy_rx"                                                        -->
    <!--                value_type         = "bool"                                                                -->
    <!--                description        = "If checked, this enables the automatic calibration logic in the hard D-PHY block. Otherwise, the PHY will use -->
    <!--                                      a pre-determined deskew delay value. "                               -->
    <!--                title              = "automatic calibration logic in hard PHY block"                       -->
    <!--                bool_value_mapping =  "('0b00000000000000000000000000000000',                              -->
    <!--                                        '0b10000000001000000000000000000000')"                             -->
    <!--                value_expr         = "False if (1500 >= RX_LINE_RATE) else True"                           -->
    <!--                editable           = "(1500 >= RX_LINE_RATE) and (DPHY_RX_IP == 'MIXEL') "                 -->
    <!--                hidden             = "(DPHY_RX_IP == 'LATTICE')"                                           -->
    <!--                group2             = "Advanced"                                                            -->
    <!-- />                                                                                                        -->

    
    <lsccip:setting id                 = "DATA_SETTLE_CYC_EN"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Customize Data Settle Cycle"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "DPHY_RX_IP == 'LATTICE' or CIL_BYPASS" 
                    hidden             = "not CIL_BYPASS"
                    description        = "Enable the customization of the Data Settle Cycle parameter, when CIL Bypass is checked."
                    group1             = "Timing Parameter"
    />
    <!--            value_range        = "(value_expr_settle_cyc_range(DPHY_RX_IP,BYTECLK_MHZ, RX_GEAR, 0),value_expr_settle_cyc_range(DPHY_RX_IP,BYTECLK_MHZ, RX_GEAR, 1))" -->
    <lsccip:setting id                 = "DATA_SETTLE_CYC"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Data Settle Cycle"
                    value_expr         = "(value_expr_data_settle_cyc(BYTECLK_MHZ, RX_GEAR,DPHY_RX_IP,RX_FIFO_TYPE))"
                    editable           = "DATA_SETTLE_CYC_EN"
                    value_range        = "(0, 255)"
                    drc                = "ext_d_hssettle_drc((DATA_SETTLE_CYC if CIL_BYPASS else (T_DATA_SETTLE_INT+1)),
                                                             (BYTECLK_MHZ if CIL_BYPASS else SYNCCLK_MHZ),RX_GEAR,DPHY_RX_IP,RX_LINE_RATE,DATA_SETTLE_CYC_EN,CIL_BYPASS)"
                    hidden             = "not CIL_BYPASS"
                    description        = "This parameter corresponds to the tHS_SETTLE timing parameter as defined in the MIPI D-PHY specification. The value is in the unit of clk_byte_o clock cycle for Soft D-PHY or clk_byte_fr_i clock cycle for Hard D-PHY with CIL Bypass. Refer to IP user guide for guidance." 
                    group1             = "Timing Parameter"
    />
    <lsccip:setting id                 = "T_DATA_SETTLE_EN"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Customize CIL Data Settle"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    hidden             = "CIL_BYPASS"
                    description        = "tHS-SETTLE range is from (82ns+6UI) to (145ns+10UI). It is recommended to choose a tHS-SETTLE value away from the boundaries. "
                    group1             = "Timing Parameter"
    />
    <!--            value_range        = "(value_expr_t_data_settle(RX_GEAR, BYTECLK_MHZ, SYNCCLK_MHZ, 0),value_expr_t_data_settle(RX_GEAR,BYTECLK_MHZ, SYNCCLK_MHZ, 3))" -->
    <lsccip:setting id                 = "T_DATA_SETTLE_INT"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "CIL Data Settle"
                    value_expr         = "value_expr_t_data_settle(RX_GEAR, BYTECLK_MHZ, SYNCCLK_MHZ, 1)"
                    hidden             = "CIL_BYPASS"
                    value_range        = "(0, 63)"
                    editable           = "T_DATA_SETTLE_EN"
                    description        = "Number of sync_clk_i cycles the IP will ignore the data lanes to mask the LP-to-HS transition effects." 
                    group1             = "Timing Parameter"
    />
    <lsccip:setting id                 = "T_DATA_SETTLE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    value_expr         = "value_expr_int_to_bin(T_DATA_SETTLE_INT)"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Timing Parameter"
    />
    <lsccip:setting id                 = "T_CLK_SETTLE_EN"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Customize CIL Clock Settle"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    hidden             = "CIL_BYPASS"
                    description        = "tCLK-SETTLE range is from 95ns to 300ns. It is recommended to choose a tCLK-SETTLE value away from the boundaries. "
                    group1             = "Timing Parameter"
    />
    <!--            value_range        = "((value_expr_t_clk_settle(RX_GEAR,SYNCCLK_MHZ,95)-1),(value_expr_t_clk_settle(RX_GEAR,SYNCCLK_MHZ,300)+1))"  -->
    <lsccip:setting id                 = "T_CLK_SETTLE_INT"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "CIL Clock Settle"
                    value_expr         = "value_expr_t_clk_settle(RX_GEAR, SYNCCLK_MHZ,150)"
                    hidden             = "CIL_BYPASS"
                    value_range        = "(1, 63)"
                    editable           = "T_CLK_SETTLE_EN"
                    description        = "Number of sync_clk_i cycles the IP will ignore the clock lanes to mask the LP-to-HS transition effects." 
                    group1             = "Timing Parameter"
    />
    <lsccip:setting id                 = "T_CLK_SETTLE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    value_expr         = "value_expr_int_to_bin(T_CLK_SETTLE_INT)"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Timing Parameter"
    />

    <lsccip:setting id                 = "DYN_DATSETTLE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Configurable Data Settle Count"
                    bool_value_mapping = "('ON', 'OFF')"
                    editable           = "CIL_BYPASS and not LMMI"
                    value_expr         = "False if (CIL_BYPASS or LMMI) else ''"
                    hidden             = "not CIL_BYPASS"
                    default            = "False"
                    group1             = "Timing Parameter"
                    description        = "When checked, an input bus rxcsr_datsettlecyc_i is available when D-PHY RX IP = “Soft D-PHY” or CIL Bypass is checked. You can adjust the tHS-SETTLE timer value without generating a new bitstream."
    />
    
    <lsccip:setting id                 = "FIFO_DEPTH"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Lane Aligner FIFO Depth"
                    value_expr         = "4"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Soft IP Implementation Settings"
    />

    <lsccip:setting id                 = "FIFO_TYPE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Lane Aligner FIFO_TYPE"
                    options            = "['HARD_IP', 'LUT']"
                    default            = "HARD_IP"
                    hidden             = "True"
                    editable           = "False"
                    group1             = "Soft IP Implementation Settings"
    />


    <!-- RX_FIFO -->
    <lsccip:setting id                 = "RX_FIFO"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "RX_FIFO Enable"
                    description        = "Instantiates a FIFO between the D-PHY high speed
                                          data strobe and the freerunning byteclock, clk_byte_fr_i. 
                                          This buffers all the high-speed packets, including the trail.
                                          For Soft D-PHY, this also includes the hs-zero bits." 
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "True"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "DPHY_RX_IP == 'LATTICE'"
                    group2             = "RX_FIFO Settings"
    />
    
    <lsccip:setting id                 = "RX_FIFO_TYPE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Type"
                    options            = "['PINGPONG', 'QUEUE', 'SINGLE']"
                    default            = "PINGPONG"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "RX_FIFO"
                    group2             = "RX_FIFO Settings"
                    description        = "Type of the FIFO implemented. Refer to RX FIFO Settings section
                                          of IP User Guide for details."
    />

    <lsccip:setting id                 = "RX_FIFO_IMPL_INPUT"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Implementation"
                    options            = "['EBR', 'LUT']"
                    default            = "EBR"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "RX_FIFO"
                    group2             = "RX_FIFO Settings"
                    description        = "Selects the memory implementation of the FIFO."
    />

    <lsccip:setting id                 = "RX_FIFO_IMPL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "RX FIFO Implementation"
                    value_expr         = "'HARD_IP' if (RX_FIFO_IMPL_INPUT == 'EBR' 
                                                        and ((RX_FIFO_TYPE == 'SINGLE' 
                                                              and FR_FIFO_CLKMODE == 'SC') 
                                                            or FAMILY != 'LAV-AT'))
                                                    else RX_FIFO_IMPL_INPUT"
                    default            = "HARD_IP"
                    hidden             = "True"
                    editable           = "False"
                    group2             = "RX_FIFO Settings"
                    description        = "Selects the memory implementation of the FIFO."
    />

    <lsccip:setting id                 = "RX_FIFO_DEPTH"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Depth"
                    options            = "ext_p_name_options(15 if RX_FIFO_IMPL_INPUT == 'EBR' else 8)"
                    default            = "256"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "RX_FIFO"
                    group2             = "RX_FIFO Settings"
                    description        = "Selects the memory depth of the FIFO."
    />

    
    <lsccip:setting id                 = "NUM_QUE_ENT"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Number of Queue Entries"
                    options            = "ext_p_name_options(4)"
                    default            = "4"
                    hidden             = "RX_FIFO_TYPE != 'QUEUE' or (DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS)"
                    editable           = "RX_FIFO_TYPE == 'QUEUE' and RX_FIFO"
                    group2             = "RX_FIFO Settings"
                    description        = "Determines the amount of Queue Entries available for the RX_FIFO."
    />

    <lsccip:setting id                 = "RX_FIFO_PKT_DLY"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Default FIFO Read Delay"
                    description        = "If the value is set to 0, the entire high speed D-PHY packets 
                                          are stored before reading from the RX_FIFO.
                                          Otherwise, this value sets the number of cycles of the clk_byte_fr_i  
                                          before reading from the RX_FIFO starting from the deassertion of the fifo_empty signal.
                                          If reconfiguration is intended, please note that initial packet (for SINGLE) and initial 
                                          2 packets (for PINGPONG) after reset will always have the Default FIFO Read Delay before
                                          IP loads whatever value the delay is reconfigured to. "
                    value_expr         = "1 if not RX_FIFO else 8"
                    value_range        = "(0,16384)"
                    default            = "8"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "RX_FIFO_TYPE != 'QUEUE' and RX_FIFO"
                    group2             = "RX_FIFO Settings"
    />

    <lsccip:setting id                 = "DYN_RXFIFO_PKTDLY"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Configurable FIFO Read Delay"
                    bool_value_mapping = "('ON', 'OFF')"
                    editable           = "CIL_BYPASS and not LMMI and RX_FIFO_TYPE != 'QUEUE' and RX_FIFO"
                    default            = "False"
                    group2             = "RX_FIFO Settings"
                    description        = "When this is checked, an input bus rxcsr_rxfifo_pktdly_i is available to adjust the 
                                          delay before the contents of the RX_FIFO is read. Maximum value allowed is dependent
                                          on the Default FIFO Read Delay set."
    />

    <lsccip:setting id                 = "RX_FIFO_CTR_WIDTH"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Counter Width"
                    description        = "if the RX_FIFO is configured as QUEUE type, this parameter is the width of the counter 
                                          that tracks the number of write cycles per high speed transaction. 
                                          This should accommodate the maximum length of a high speed transaction, including the
                                          hs-zero and the trail bits.  Otherwise, this 
                                          is the width of the read delay counter in the clk_byte_fr_i domain." 
                    value_range        = "(1,log2_val(RX_FIFO_DEPTH)) if RX_FIFO_TYPE == 'QUEUE' else (1,log2_val(RX_FIFO_PKT_DLY))"                                          
                    value_expr         = "log2_val(RX_FIFO_DEPTH) if RX_FIFO_TYPE == 'QUEUE' else log2_val(RX_FIFO_PKT_DLY)"
                    hidden             = "RX_FIFO_TYPE != 'QUEUE' or (DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS)"
                    editable           = "RX_FIFO and (RX_FIFO_TYPE == 'QUEUE')"
                    group2             = "RX_FIFO Settings"
    />

    <lsccip:setting id                 = "FR_FIFO_CLKMODE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Clock Mode"
                    options            = "['SC', 'DC']"
                    default            = "DC"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
                    editable           = "RX_FIFO_TYPE == 'SINGLE' and RX_FIFO and DPHY_RX_IP == 'LATTICE'"
                    group2             = "RX_FIFO Settings"
                    description        = "Determines if the FIFO is implemented in Single Clock and Dual Clock. This value is editable when Type = “SINGLE” and RX_FIFO is checked. The clock mode is always “DC” when D-PHY RX IP = “Hard D-PHY”."
    />

    <lsccip:setting id                 = "FIFO_IF"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Write/Read Command"
                    options            = "['CENTERED', 'ALIGNED']"
                    value_expr         = "'CENTERED' if (DPHY_RX_IP == 'MIXEL') else 'ALIGNED'"
                    hidden             = "True"
                    editable           = "RX_FIFO and DPHY_RX_IP == 'MIXEL'"
                    group2             = "RX_FIFO Settings"
    />

    <lsccip:setting id                 = "RX_FIFO_MISC"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Misc Signals"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    hidden             = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"                 
                    editable           = "RX_FIFO"
                    group2             = "RX_FIFO Settings"
                    description        = "When checked, this shows the fifo_empty and fifo_full status signals at the top level module."
    />
    
    <!-- DELAYB manual adjustment -->
    <lsccip:setting id                 = "DELAYB_DELMODE"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Delay Mode"
                    options            = "[('Edge Clock Centered', 'ECLK_CENTERED'),
                                           ('User Defined', 'USER_DEFINED')]"
                    value_expr         = "'USER_DEFINED' if (CTRL_DYNDEL) else 'ECLK_CENTERED'"
                    default            = "ECLK_CENTERED"
                    editable           = "not (CTRL_DYNDEL)"
                    hidden             = "DPHY_RX_IP == 'MIXEL' or FAMILY == 'LAV-AT'"
                    group1             = "Delay Cell Settings"
                    group2             = "Soft PHY"
                    description        = "“Edge Clock Centered” uses a predetermined static delay value of the delay cells. The value is used to center align the D-PHY data with respect to the D-PHY clock edges. “User Defined” allows for customization of the delay cell settings."
    />
    
    <lsccip:setting id                 = "DELAYB_COARSEDEL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Coarse Delay"
                    value_expr         = "ext_get_delayb_del_value(RX_LINE_RATE/2.0, 'DELAYB_COARSEDEL')"
                    options            = "[('0 ns', '0NS'),
                                           ('0.80 ns', '0P8NS'),
                                           ('1.60 ns', '1P6NS')]"
                    hidden             = "DPHY_RX_IP == 'MIXEL' or FAMILY == 'LAV-AT'"
                    editable           = "DELAYB_DELMODE == 'USER_DEFINED'"
                    group1             = "Delay Cell Settings"
                    group2             = "Soft PHY"
                    description        = "Selects between 0, 0.8, or 1.6 ns coarse delay."
    />

    <lsccip:setting id                 = "DELAYB_DELVAL_IN"
                    type               = "input"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "int"
                    title              = "Fine Delay"
                    hidden             = "DPHY_RX_IP == 'MIXEL' or FAMILY == 'LAV-AT' or DELAYB_DELMODE != 'USER_DEFINED'"
                    editable           = "DELAYB_DELMODE == 'USER_DEFINED'"
                    value_range        = "(0, 127)"
                    default            = "0"
                    group1             = "Delay Cell Settings"
                    group2             = "Soft PHY"
                    description        = "Each step value adds 12.5 ps delay on the data lanes."
    />

    <lsccip:setting id                 = "DELAYB_DELVAL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "string"
                    title              = "Fine Delay"
                    value_expr         = "DELAYB_DELVAL_IN if (DELAYB_DELMODE == 'USER_DEFINED') else 
                                          ext_get_delayb_del_value(RX_LINE_RATE/2.0, 'DELAYB_DELVAL')"
                    hidden             = "DPHY_RX_IP == 'MIXEL' or FAMILY == 'LAV-AT' or DELAYB_DELMODE == 'USER_DEFINED'"
                    editable           = "False"
                    group1             = "Delay Cell Settings"
                    group2             = "Soft PHY"
                    description        = "Each step value adds 12.5 ps delay on the data lanes."
    />

    <lsccip:setting id                 = "CTRL_DYNDEL"
                    type               = "param"
                    conn_mod           = "lscc_dphy_rx"
                    value_type         = "bool"
                    title              = "Enable Dynamic Delay Control"
                    bool_value_mapping = "('ON', 'OFF')"
                    default            = "False"
                    editable           = "True"
                    hidden             = "DPHY_RX_IP == 'MIXEL' or FAMILY == 'LAV-AT'"
                    group1             = "Delay Cell Settings"
                    group2             = "Soft PHY"
                    description        = "When checked, delay cell with dynamic adjustment
                                          feature is used instead of a STATIC delay cell.
                                          Ports that dynamically control the fine and 
                                          course delay are available in the soft IP."
    />

  </lsccip:settings>

  <!-- ==================================================================== -->
  <!-- ==================================================================== -->
  <lsccip:ports>
    <!-- LMMI Interface -->
    <lsccip:port name      = "lmmi_clk_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_clk_i"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_resetn_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_resetn_i"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_wdata_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_wdata_i"
                 range     = "(7, 0)"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_rdata_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_rdata_o"
                 range     = "(7, 0)"
                 dangling  = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_rdata_valid_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_rdata_valid_o"
                 dangling  = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_wr_rdn_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_wr_rdn_i"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_offset_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_offset_i"
                 range     = "(7, 0)"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_request_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_request_i"
                 stick_low = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />

    <lsccip:port name      = "lmmi_ready_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lmmi_ready_o"
                 dangling  = "not LMMI"
                 bus_interface = "LMMI_SLV"
    />
    
    <!--lsccip:port name      = "rxcsr_vcx_on_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_vcx_on_i"
                 stick_value  = "ext_vcx_port_val(LMMI,VCX_ON)"
    /-->
    <lsccip:port name      = "rxcsr_vcx_on_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_vcx_on_i"
                 stick_low  = "LMMI or not PARSER"
    />    
    
    <!--lsccip:port name      = "rxcsr_dropnull_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_dropnull_i"
                 stick_value  = "ext_vcx_port_val(LMMI,DROP_NULL)"
    /-->    
    <lsccip:port name      = "rxcsr_dropnull_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_dropnull_i"
                 stick_low = "LMMI or not PARSER "
    />  											   

    <lsccip:port name      = "rxcsr_actvln_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_actvln_i"
                 range     = "(1, 0)"
                 stick_value  = "ext_dynlane_val(LMMI,DYNAMIC_RECONFIG,NUM_RX_LANE)"
    /> 
    
    <lsccip:port name      = "rxcsr_datawidth_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_datawidth_i"
                 stick_value  = "ext_dyngear_val(LMMI,DYNAMIC_RECONFIG,RX_GEAR_INPUT,DPHY_RX_IP)"
    />
    
    <lsccip:port name      = "rxcsr_datsettlecyc_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_datsettlecyc_i"
                 range     = "(7, 0)"
                 stick_value = "ext_datsettlecyc_port_val(DATA_SETTLE_CYC,DYN_DATSETTLE)"
    />    
    
    <lsccip:port name      = "rxcsr_rxfifo_pktdly_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxcsr_rxfifo_pktdly_i"
                 range     = "(15, 0)"
                 stick_value = "ext_rxfifo_pktdly_port_val(RX_FIFO_PKT_DLY,DYN_RXFIFO_PKTDLY,RX_FIFO)"
    />    


    <!-- AXI4-Stream Interface -->
    <lsccip:port name      = "axis_tvalid_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "axis_tvalid_o"
                 dangling  = "not AXI4"
                 bus_interface = "AXI4S_M0"
    />

    <lsccip:port name      = "axis_tdata_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "axis_tdata_o"
                 range     = "(NUM_RX_LANE * RX_GEAR_INPUT +
                                  DATA_R_WIDTH - 1 , 0)"
                 dangling  = "not AXI4"
                 bus_interface = "AXI4S_M0"
    />

    <lsccip:port name      = "axis_tready_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "axis_tready_i"
                 stick_low = "not AXI4"
                 bus_interface = "AXI4S_M0"
    />

    <!-- PLL Lock -->
    <lsccip:port name      = "pll_lock_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "pll_lock_i"
                 stick_low = "DPHY_RX_IP == 'MIXEL'"
    />

    <lsccip:port name      = "sync_clk_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "sync_clk_i"
                 stick_low = "DPHY_RX_IP == 'MIXEL' and CIL_BYPASS"
    />

    <lsccip:port name      = "sync_rst_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "sync_rst_i"
                 stick_low = "DPHY_RX_IP == 'MIXEL' and CIL_BYPASS"
    />

    <lsccip:port name      = "ready_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ready_o"
                 dangling  = "DPHY_RX_IP == 'MIXEL'"
    />

    <!-- Output Clock -->
    <lsccip:port name      = "clk_byte_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_byte_o"
    />

    <lsccip:port name      = "clk_byte_hs_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_byte_hs_o"
    />

    <!-- Input Clocks -->
    <lsccip:port name      = "clk_lp_ctrl_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_lp_ctrl_i"
                 stick_low = "RX_CLK_MODE == 'HS_ONLY' or (DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS)"
    />

    <lsccip:port name      = "clk_byte_fr_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_byte_fr_i"
    />

    <!-- Input Resets -->
    <lsccip:port name      = "reset_n_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "reset_n_i"
                 stick_low = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"

    />

    <lsccip:port name      = "reset_lp_n_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "reset_lp_n_i"
                 stick_low = "RX_CLK_MODE == 'HS_ONLY' or (DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS)"
    />

   <!--  <lsccip:port name      = "reset_byte_n_i" -->
   <!--               dir       = "in"             -->
   <!--               conn_mod  = "lscc_dphy_rx"   -->
   <!--               conn_port = "reset_byte_n_i" -->
   <!--  />                                        -->

    <lsccip:port name      = "reset_byte_fr_n_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "reset_byte_fr_n_i"
    />

    <!-- MIPI Interface -->
    <lsccip:port name      = "clk_p_io"
                 dir       = "inout"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_p_io"
    />

    <lsccip:port name      = "clk_n_io"
                 dir       = "inout"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "clk_n_io"
    />

    <lsccip:port name      = "d_p_io"
                 dir       = "inout"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "d_p_io"
                 range     = "(NUM_RX_LANE - 1, 0)"
    />

    <lsccip:port name      = "d_n_io"
                 dir       = "inout"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "d_n_io"
                 range     = "(NUM_RX_LANE - 1, 0)"
    />

    <!-- Outputs to Fabric for Low Power Signaling -->
    <lsccip:port name      = "lp_d_rx_p_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_d_rx_p_o"
                 range     = "(NUM_RX_LANE - 1, 0)"
                 dangling  = "not CIL_BYPASS"
    />

    <lsccip:port name      = "lp_d_rx_n_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_d_rx_n_o"
                 range     = "(NUM_RX_LANE - 1, 0)"
                 dangling  = "not CIL_BYPASS"
    />

    <lsccip:port name      = "bd_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "bd_o"
                 range     = "(NUM_RX_LANE * 8 - 1, 0)"
                 dangling  = "not PARSER or RX_GEAR_INPUT != 8"
    />

    <lsccip:port name      = "cd_clk_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "cd_clk_o"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "cd_d0_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "cd_d0_o"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "hs_d_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "hs_d_en_o"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "hs_sync_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "hs_sync_o"
                 dangling  = "not CIL_BYPASS"
    />

    <lsccip:port name      = "lp_hs_state_clk_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_hs_state_clk_o"
                 range     = "(1, 0)"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "lp_hs_state_d_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_hs_state_d_o"
                 range     = "(1, 0)"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "term_clk_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "term_clk_en_o"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <lsccip:port name      = "term_d_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "term_d_en_o"
                 range     = "(NUM_RX_LANE - 1, 0)"
                 dangling  = "not MISC_ON or not CIL_BYPASS"
    />

    <!-- Outputs When AXI4-Stream Disabled -->
    <!-- When Parser ON -->
    <lsccip:port name      = "payload_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "payload_en_o"
                 dangling  = "AXI4 or not PARSER"
    />

    <lsccip:port name      = "payload_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "payload_o"
                 range     = "(NUM_RX_LANE * RX_GEAR_INPUT - 1, 0)"
                 dangling  = "AXI4 or not PARSER"
    />

    <lsccip:port name      = "dt_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dt_o"
                 range     = "(5, 0)"
                 dangling  = "AXI4 or not PARSER"
    />

    <lsccip:port name      = "vc_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "vc_o"
                 range     = "(1, 0)"
                 dangling  = "AXI4 or not PARSER"
    />
    
    <!--lsccip:port name      = "vcx_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "vcx_o"
                 range     = "(1, 0)"
                 dangling  = "(RX_TYPE == 'DSI') or not PARSER or (VCX_ON == 'OFF')"
    /--> 
	<lsccip:port name      = "vcx_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "vcx_o"
                 range     = "(1, 0)"
                 dangling  = "AXI4 or not PARSER"
    />
    <lsccip:port name      = "wc_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "wc_o"
                 range     = "(15, 0)"
                 dangling  = "AXI4 or not PARSER"
    />

    <lsccip:port name      = "ecc_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ecc_o"
                 range     = "(5, 0)"
                 dangling  = "AXI4 or not PARSER"
    />
    
    <!-- start: new ports for error checking  -->
        <!--lsccip:port name                  = "payload_bytevld_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(7, 0)" 
                     conn_port             = "payload_bytevld_o" 
                     dangling              = "not PARSER or BACK2BACK == 'ON'"
        /-->
		<lsccip:port name                  = "payload_bytevld_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(7, 0)" 
                     conn_port             = "payload_bytevld_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <!--lsccip:port name                  = "payload_crc_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(15, 0)" 
                     conn_port             = "payload_crc_o" 
                     dangling              = "not PARSER or BACK2BACK == 'ON'"
        /-->
        <lsccip:port name                  = "payload_crc_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(15, 0)" 
                     conn_port             = "payload_crc_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <!--lsccip:port name                  = "payload_crcvld_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "payload_crcvld_o" 
                     dangling              = "not PARSER or BACK2BACK == 'ON'"
        /-->
        <lsccip:port name                  = "payload_crcvld_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "payload_crcvld_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <!-- dangling  = "not PARSER or not CRC_CHECK"  -->
        <!--lsccip:port name                  = "crc_check_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "crc_check_o" 
                     dangling              = "not PARSER or not CRC_CHECK"
        /-->
		<lsccip:port name                  = "crc_check_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "crc_check_o" 
                     dangling              = "AXI4 or not CRC_CHECK"
        />
        
        <!-- dangling  = "not PARSER or not CRC_CHECK"  -->
        <!--lsccip:port name                  = "crc_error_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "crc_error_o" 
                     dangling              = "not PARSER or not CRC_CHECK"
        /-->
		<lsccip:port name                  = "crc_error_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "crc_error_o" 
                     dangling              = "AXI4 or not CRC_CHECK"
        />
    <!-- JAS: added condition that these ports is not available for DSI  -->
        <lsccip:port name                  = "ecc_check_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "ecc_check_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <lsccip:port name                  = "ecc_byte_error_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "ecc_byte_error_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <lsccip:port name                  = "ecc_1bit_error_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "ecc_1bit_error_o" 
                     dangling              = "AXI4 or not PARSER"
        />
        <lsccip:port name                  = "ecc_2bit_error_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     conn_port             = "ecc_2bit_error_o" 
                     dangling              = "AXI4 or not PARSER"
        />
    <!-- end: new ports for error checking  -->
    <!-- start: new ports for dynamic reconfiguration  -->
        <lsccip:port name                  = "dphy_rxdatawidth_hs_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(1, 0)" 
                     conn_port             = "dphy_rxdatawidth_hs_o" 
                     dangling              = "not PARSER"
        />
        <lsccip:port name                  = "dphy_cfg_num_lanes_o" 
                     dir                   = "out" 
                     conn_mod              = "lscc_dphy_rx" 
                     range                 = "(1, 0)" 
                     conn_port             = "dphy_cfg_num_lanes_o" 
                     dangling              = "not PARSER"
        />
    <!-- end: new ports for dynamic reconfiguration  -->	
	
	
    <lsccip:port name      = "dt2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dt2_o"
                 range     = "(5, 0)"
                 dangling  = "AXI4 or not PARSER or
                                 NUM_RX_LANE * RX_GEAR_INPUT != 64"
    />

    <lsccip:port name      = "vc2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "vc2_o"
                 range     = "(1, 0)"
                 dangling  = "AXI4 or not PARSER or
                                  NUM_RX_LANE * RX_GEAR_INPUT != 64"
    />

    <lsccip:port name      = "wc2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "wc2_o"
                 range     = "(15, 0)"
                 dangling  = "AXI4 or not PARSER or
                                  NUM_RX_LANE * RX_GEAR_INPUT != 64"
    />

    <lsccip:port name      = "ecc2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ecc2_o"
                 range     = "(5, 0)"
                 dangling  = "AXI4 or not PARSER or
                                  NUM_RX_LANE * RX_GEAR_INPUT != 64"
    />

    <!-- When Parser OFF -->
    <lsccip:port name      = "bd0_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "bd0_o"
                 range     = "(RX_GEAR_INPUT - 1, 0)"
                 dangling  = "AXI4 or PARSER"
    />

    <lsccip:port name      = "bd1_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "bd1_o"
                 range     = "(RX_GEAR_INPUT - 1, 0)"
                 dangling  = "AXI4 or PARSER or
                                  NUM_RX_LANE in [1]"
    />

    <lsccip:port name      = "bd2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "bd2_o"
                 range     = "(RX_GEAR_INPUT - 1, 0)"
                 dangling  = "AXI4 or PARSER or
                                  NUM_RX_LANE in [1, 2]"
    />

    <lsccip:port name      = "bd3_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "bd3_o"
                 range     = "(RX_GEAR_INPUT - 1, 0)"
                 dangling  = "AXI4 or PARSER or
                                  NUM_RX_LANE in [1, 2, 3]"
    />

    <lsccip:port name      = "capture_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "capture_en_o"
                 dangling  = "AXI4 or PARSER"
    />

    <!-- Native Interface -->
    <!-- stick_low = "LMMI or  (not PARSER) or                   -->
    <!--            (not REF_DT_STRING == 'from ref_dt_i port')" -->
    <!--lsccip:port name      = "ref_dt_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ref_dt_i"
                 range     = "(5, 0)"
                 stick_value = "ext_refdt_port_val(LMMI,PARSER,REF_DT_STRING,REF_DT)"
    /-->
	<lsccip:port name      = "ref_dt_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ref_dt_i"
                 range     = "(5, 0)"
                 stick_low = "LMMI or not PARSER"
    />
    
    <lsccip:port name      = "tx_rdy_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "tx_rdy_i"
                 stick_low = "DPHY_RX_IP == 'MIXEL' and not CIL_BYPASS"
    />

    <lsccip:port name      = "lp_d0_tx_en_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_d0_tx_en_i"
                 stick_low = "not(CIL_BYPASS) or RX_TYPE == 'CSI2'"
    />

    <lsccip:port name      = "lp_d0_tx_p_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_d0_tx_p_i"
                 stick_low = "not(CIL_BYPASS) or RX_TYPE == 'CSI2'"
    />

    <lsccip:port name      = "lp_d0_tx_n_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_d0_tx_n_i"
                 stick_low = "not(CIL_BYPASS) or RX_TYPE == 'CSI2'"
    />

    <lsccip:port name      = "pd_dphy_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "pd_dphy_i"
                 stick_low = "DPHY_RX_IP == 'LATTICE'"
    />

    <lsccip:port name      = "sp_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "sp_en_o"
                 dangling  = "not PARSER"
    />

    <lsccip:port name      = "lp_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_en_o"
                 dangling  = "not PARSER"
    />

    <lsccip:port name      = "lp_av_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp_av_en_o"
                 dangling  = "not PARSER"
    />

    <lsccip:port name      = "sp2_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "sp2_en_o"
                 dangling  = "(not PARSER) or (NUM_RX_LANE != 4 or
                                  RX_GEAR_INPUT != 16)"
    />

    <lsccip:port name      = "lp2_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp2_en_o"
                 dangling  = "(not PARSER) or (NUM_RX_LANE != 4 or
                                  RX_GEAR_INPUT != 16)"
    />


    <lsccip:port name      = "lp2_av_en_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lp2_av_en_o"
                 dangling  = "(not PARSER) or (NUM_RX_LANE != 4 or
                                  RX_GEAR_INPUT != 16)"
    />

    <lsccip:port name      = "hs_en0_settle_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "hs_en0_settle_o"
                 dangling  = "True"
    />

    <lsccip:port name      = "rxdatsyncfr_state_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxdatsyncfr_state_o"
                 range     = "(1, 0)"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxemptyfr0_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxemptyfr0_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxemptyfr1_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxemptyfr1_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxfullfr0_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxfullfr0_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxfullfr1_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxfullfr1_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxque_curstate_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxque_curstate_o"
                 range     = "(1, 0)"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxque_empty_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxque_empty_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "rxque_full_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "rxque_full_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "fifo_dly_err_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "fifo_dly_err_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "fifo_undflw_err_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "fifo_undflw_err_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />

    <lsccip:port name      = "fifo_ovflw_err_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "fifo_ovflw_err_o"
                 dangling  = "not(RX_FIFO_MISC)"
    />
    
    <lsccip:port name      = "skewcal_det_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "skewcal_det_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "DESKEW_EN == 'DISABLED'"
    />
    <lsccip:port name      = "skewcal_done_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "skewcal_done_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "(DESKEW_EN == 'DISABLED') or (DESKEW_EN == 'ENABLED' and CIL_BYPASS)"
    />
    <lsccip:port name      = "err_syncdet_soft_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_syncdet_soft_o"
                 range     = "(3 , 0)"
                 dangling  = "1" 
    />  

    <lsccip:port name      = "edgemon_done_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "edgemon_done_o"
                 dangling  = "(FAMILY != 'LAV-AT')"
    />

    <lsccip:port name      = "dll_freeze_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dll_freeze_o"
                 dangling  = "1"
    />

    <lsccip:port name      = "dll_code_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dll_code_i"
                 range     = "(8 , 0)"
                 stick_low = "not (DYN_DEL_EN and not DDRDLL_EN) or FAMILY != 'LAV-AT'"
    />

    <lsccip:port name      = "dll_lock_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dll_lock_i"
                 stick_low = "not (DYN_DEL_EN and not DDRDLL_EN) or FAMILY != 'LAV-AT'"
    />

    <lsccip:port name      = "dll_code_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dll_code_o"
                 range     = "(8 , 0)"
                 dangling  = "not (DYN_DEL_EN and DDRDLL_EN and DDRDLL_SHARE) or FAMILY != 'LAV-AT'"
    />

    <lsccip:port name      = "dll_lock_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "dll_lock_o"
                 dangling  = "not (DYN_DEL_EN and DDRDLL_EN and DDRDLL_SHARE) or FAMILY != 'LAV-AT'"
    />

  <!-- Error Flags from Hard D-PHY -->  
  <!--   dangling  = "not(RX_FIFO_MISC and (DPHY_RX_IP == 'MIXEL'))"  -->  
    <lsccip:port name      = "err_ctrl_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_ctrl_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "1" 
    /> 

    <lsccip:port name      = "err_esc_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_esc_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "1" 
    /> 

    <lsccip:port name      = "err_soths_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_soths_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "1" 
    />     
    
    <lsccip:port name      = "err_syncesc_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_syncesc_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "1" 
    /> 

    <lsccip:port name      = "err_sotsynchs_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "err_sotsynchs_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "1" 
    /> 
	
<!--    hard dphy debug ports                           -->
<!--    Low Power Receiver Enable Signal                -->
    <lsccip:port name      = "lane0_stop_state"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "lane0_stop_state"
                 dangling  = "True"
    />

    <lsccip:port name      = "ude5d0rn"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ude5d0rn"
                 dangling  = "True"
    />
    <lsccip:port name      = "ude6d1rn"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ude6d1rn"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "ude7d2rn"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "ude7d2rn"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1tde0d3"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1tde0d3"
                 dangling  = "True"
    /> 
	<!--    High Speed Receiver Enable Signal               -->
    <lsccip:port name      = "uctxupsc"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "uctxupsc"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "utxskd0n"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "utxskd0n"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1txsk"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1txsk"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2txskc"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2txskc"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u3txskc"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3txskc"
                 dangling  = "True"
    /> 
    <!--    DESERIALIZER enable                             -->
    <lsccip:port name      = "utxrd0en"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "utxrd0en"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1txreq"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1txreq"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2txreq"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2txreq"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u3txreq"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3txreq"
                 dangling  = "True"
    /> 
                                 
    <!--   LP_TX power down inputs                       -->
    <lsccip:port name      = "u2tde4ck"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2tde4ck"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2tde5d0"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2tde5d0"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2tde6d1"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2tde6d1"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2tde7d2"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2tde7d2"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u3tde0d3"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3tde0d3"
                 dangling  = "True"
    /> 
    <!--    contention detection                            -->
    <lsccip:port name      = "u1re0d"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1re0d"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1re1cn"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1re1cn"
                 dangling  = "True"
    /> 
    <!--    high speed receive data valid                   -->
    <lsccip:port name      = "urxvdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "urxvdhs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1rxvdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1rxvdhs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2rxvdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2rxvdhs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u3rxvdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3rxvdhs"
                 dangling  = "True"
    /> 
<!--    dphy high speed data output [RX_GEAR-1:0]       -->
    <lsccip:port name      = "urxdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "urxdhs"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "True" 
    />
    <lsccip:port name      = "u1rxdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1rxdhs"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "True" 
    />
    <lsccip:port name      = "u2rxdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2rxdhs"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "True" 
    />
    <lsccip:port name      = "u3rxdhs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3rxdhs"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "True" 
    />

<!--    B8 Sync Pattern detect (from hard deserializer) -->
    <lsccip:port name      = "urxshs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "urxshs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u1rxshs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u1rxshs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u2rxshs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u2rxshs"
                 dangling  = "True"
    /> 
    <lsccip:port name      = "u3rxshs"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "u3rxshs"
                 dangling  = "True"
    /> 
<!--    end hard dphy debug ports                       -->	
<!--    other debug ports                       -->	
    <lsccip:port name      = "fifo_full_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "fifo_full_o"
                 dangling  = "True"
    /> 

    <lsccip:port name      = "fifo_empty_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "fifo_empty_o"
                 dangling  = "True"
    /> 

    <lsccip:port name      = "vcx2_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "vcx2_o"
                 range     = "(1 , 0)"
                 dangling  = "True"
    /> 

<!--    Dynamic Delay Control signals  -->
    <lsccip:port name      = "data_loadn_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "data_loadn_i"
                 stick_low = "not (CTRL_DYNDEL)" 
    />

    <lsccip:port name      = "data_move_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "data_move_i"
                 stick_low = "not (CTRL_DYNDEL)" 
    />

    <lsccip:port name      = "data_dir_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "data_dir_i"
                 stick_low = "not (CTRL_DYNDEL)" 
    />

    <lsccip:port name      = "data_coarsedly_i"
                 dir       = "in"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "data_coarsedly_i"
                 range     = "(1 , 0)"
                 stick_low = "not (CTRL_DYNDEL)" 
    />

    <lsccip:port name      = "data_cflag_o"
                 dir       = "out"
                 conn_mod  = "lscc_dphy_rx"
                 conn_port = "data_cflag_o"
                 range     = "(NUM_RX_LANE -1 , 0)"
                 dangling  = "not (CTRL_DYNDEL)" 
    />

  </lsccip:ports>

  <lsccip:outFileConfigs>
    <lsccip:fileConfig name="wrapper" file_suffix="sv" file_description="top_level_system_verilog"></lsccip:fileConfig>
  </lsccip:outFileConfigs>

  <xi:include href="bus_interface.xml" parse="xml" /> 
  <xi:include href="memory_map.xml" parse="xml" />

  <lsccip:componentGenerators>
	<lsccip:componentGenerator>
	  <lsccip:name>ip_constraint_setup</lsccip:name>
      <lsccip:generatorExe>eval/ip_eval_setup.py</lsccip:generatorExe>
    </lsccip:componentGenerator>
  </lsccip:componentGenerators>
</lsccip:ip>