The Lattice Semiconductor CSI-2/DSI D-PHY Receiver IP Core converts DSI or CSI-2 data to 8-bit, 16-bit, 32-bit, or 64-bit data for Lattice FPGA devices built on the Lattice Avant™, Nexus™, and Nexus 2 platforms.The CSI-2/DSI D-PHY Receiver IP Core is intended for use in applications that require a D-PHY receiver in the FPGA logic. D-PHY Rx IP includes in both the high-speed and low power modules. The payload data (image data) uses the high-speed mode whereas the control and status information are sent through low power mode. The number of D-PHY data lanes for data transmission is configurable and supported 1, 2, 3, or 4 data lanes.
Crosslink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant, Certus-N2