CSI-2/DSI D-PHY Receiver

Description

The Lattice Semiconductor CSI-2/DSI D-PHY Receiver IP Core converts DSI or CSI-2 data to 8-bit, 16-bit, 32-bit, or 64-bit data for Lattice FPGA devices built on the Lattice Avant™, Nexus™, and Nexus 2 platforms.The CSI-2/DSI D-PHY Receiver IP Core is intended for use in applications that require a D-PHY receiver in the FPGA logic. D-PHY Rx IP includes in both the high-speed and low power modules. The payload data (image data) uses the high-speed mode whereas the control and status information are sent through low power mode. The number of D-PHY data lanes for data transmission is configurable and supported 1, 2, 3, or 4 data lanes.

Devices Supported

Crosslink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant, Certus-N2

References

User Guide

Release Notes

1.9.0	IP Release Notes
1.8.0	Added Certus-N2 support.
1.7.0	Fixed functional bugs found in last release. Fixed issues with testbench. Fixed issues related to internal LMMI signal initializations. Corrected default setting of some of hard DPHY parameters. Enhanced constraint generation and implementation. Uses new IP constraint propagation method by SW. Added support for Propel. Updated port list and names. Other minor GUI fixes.
1.6.1	Fixed an issue related to setting small word count. Fixed issues in testbench. Other IP GUI fixes and enhancements.
1.6.0	Added Soft D-PHY delay cell settings in the GUI. Added support for CSI-2 Extended Virtual Channel ID. Added header ECC error check and correction. Added support for dynamic late rate reconfiguration (Hard D-PHY CIL-Enabled). Added support for LFMXO5-55T, LFMXO5-100T, and LAV-AT devices.
1.5.0	Added support for LAV-AT-E devices.
1.4.3	Removed partial encryption of dphy_rx_wrap module; no RTL source code change. Added checking of speed grade to determine the maximum supported data rate.
1.4.2	Added more clear text portion in the partially encrypted RTL to resolve syntax error getting flagged when Reveal is disabled in v1.4.1; no RTL source code change. Added checking of package type to determine the maximum supported data rate.
1.4.1	Unencrypted the hard D-PHY primitive instantiation to support Reveal insertion.
1.4.0	Fixed clock constraints in the ldc file. Fixed VCS compilation errors: - Error-[IRIBS] Illegal range in bit-select - Error-[MEAFFS] No argument for format specification Added LFMXO5-25 support
1.3.0	Fixed issue found in non-continuous clock mode (HS to LP transition detection)
1.2.0	Added CertusPro-NX support.
1.1.2	Updated INIT value of CLK_DESKEW_DLYCAL when data rate is less than or equal to 1.5 Gbps
1.1.1	Added deskew calibration support. Adjusted Soft D-PHY HS-SETTLE parameter count. Hid RX_FIFO parameters in the GUI when CIL is enabled.
1.1.0	Added support for RX lane = 3 in the Verilog testbench. Fixed hs-settle timing for Soft D-PHY. Fixed ports when LMMI is enabled. Added Certus-NX support.
1.0.1	Production release.
1.0.0	Initial release.

Limitations

This section serves as a complement of the official User Guide.

1.9.0	The IP only supports even word count for multiple DSI packets transmitted within a single HS transmission, including EoTp, Null and Blanking (when DSI Back-to-Back HS Packets == ON). When DSI Back-to-Back HS Packets == ON, ECC and CRC checks are not supported. When D-PHY RX IP == Soft D-PHY or CIL Bypass is checked, follow these guidelines: For data rates with corresponding byte clock of 30 MHz and below, the minimum duration of the tHS-PREPARE + tHS-ZERO from the D-PHY source is 145 ns + 10 x UI + 2 x TCLK_BYTE, where TCLK_BYTE is clk_byte_o for Soft D-PHY and clk_byte_fr_i for Hard D-PHY with CIL bypassed, to ensure proper detection of the Start-of-Transmit pattern. For lower data rates, ensure the duration of tLPX and tHS-TRAIL are longer than the clk_byte_fr_i period with at least 1.5x duration. Some configurations may fail Static Timing Analysis when compiling your design using LSE. If this happens, consider compiling your design using the Synopsis Synplify Pro. Some IP configurations may have slower Fmax when used in devices with slow speed grade. The following Fmax values are approximates and may vary depending on the system-level design: Nexus devices: 122 MHz for Gear 8, 111 MHz for Gear 16 Avant devices: 145 MHz AXI4-Stream interface does not support back-pressure. Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported. For Lattice Avant devices, packets may be missing after a local system reset is performed because of the current design limitation of using the delay block.
1.8.0--	The IP only supports even word count for multiple DSI packets transmitted within a single HS transmission, including EoTp, Null and Blanking (when DSI Back-to-Back HS Packets == ON). When DSI Back-to-Back HS Packets == ON, ECC and CRC checks are not supported. When D-PHY RX IP == Soft D-PHY or CIL Bypass is checked, follow these guidelines: For data rates with corresponding byte clock of 30 MHz and below, the minimum duration of the tHS-PREPARE + tHS-ZERO from the D-PHY source is 145 ns + 10 x UI + 2 x TCLK_BYTE, where TCLK_BYTE is clk_byte_o for Soft D-PHY and clk_byte_fr_i for Hard D-PHY with CIL bypassed, to ensure proper detection of the Start-of-Transmit pattern. For lower data rates, ensure the duration of tLPX and tHS-TRAIL are longer than the clk_byte_fr_i period with at least 1.5x duration. Some configurations may fail Static Timing Analysis when compiling your design using LSE. If this happens, consider compiling your design using the Synopsis Synplify Pro. Some IP configurations may have slower Fmax when used in devices with slow speed grade. The following Fmax values are approximates and may vary depending on the system-level design: Nexus devices: 122 MHz for Gear 8, 111 MHz for Gear 16 Avant devices: 145 MHz Test Coverage Limitations: SOT error for soft DPHY (addr : 0x39) is not tested. ECC feature with error scenario is not tested in DSI mode. This feature is tested only in CSI-2 mode. AXI4-Stream interface does not support back-pressure. Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported. For Lattice Avant devices, packets may be missing after a local system reset is performed because of the current design limitation of using the delay block.
1.6.1--	AXI4-Stream interface does not support back-pressure. Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported. For Lattice Avant devices, packets may be missing after a local system reset is performed because of the current design limitation of using the delay block.