The Divider IP core is a one-clock divider which completes one integer division every clock.
It supports signed or unsigned inputs and provides configurable output latency.
Crosslink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Certus-NX-RT, CertusPro-NX-RT, Avant, Certus-N2