The Divider IP core is a one-clock divider which completes one integer division every clock.
It supports signed or unsigned inputs and provides configurable output latency.
LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100, LFMXO5-25
| 1.2.0 | Added LFMXO5 support. |
| 1.1.0 | Added LFCPNX support. |
| 1.0.0 | Initial release. |