/*   ==================================================================

     >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     ------------------------------------------------------------------
     Copyright (c) 2019-2020 by Lattice Semiconductor Corporation
     ALL RIGHTS RESERVED
     ------------------------------------------------------------------

       IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™
       DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK.

       Lattice grants permission to use this code pursuant to the
       terms of the Lattice Propel License Agreement.

     DISCLAIMER:

    LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS,
    WHETHER EXPRESSED, IMPLIED, STATUTORY,
    OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR
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    AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF
    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
    LATTICE DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED HEREIN WILL MEET
    LICENSEE 'S REQUIREMENTS, OR THAT LICENSEE' S OPERATION OF ANY DEVICE,
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    OR THAT DEFECTS HEREIN WILL BE CORRECTED.
    LICENSEE ASSUMES RESPONSIBILITY FOR SELECTION OF MATERIALS TO ACHIEVE
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    LICENSEE ASSUMES THE ENTIRE RISK OF THE FILE AND ITS CONTENTS PROVING
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    ARISING OUT OF THE USE OF THIS FILE OR ITS CONTENTS,
    EVEN IF LATTICE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    LATTICE 'S SOLE LIABILITY, AND LICENSEE' S SOLE REMEDY,
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     ------------------------------------------------------------------

     ================================================================== */

#include <dp.h>

#define ERROR							1
#define NO_ERROR						0

//private APIs

unsigned char DP_RX_Video_Stream_0_MSA_Info (void);
unsigned char DP_RX_Video_Stream_1_MSA_Info (void);
unsigned char DP_RX_Video_Stream_2_MSA_Info (void);
unsigned char DP_RX_Video_Stream_3_MSA_Info (void);

unsigned char DP_RX_Main_Video_Info_Stream_0 (void);
unsigned char DP_RX_Main_Video_Info_Stream_1 (void);
unsigned char DP_RX_Main_Video_Info_Stream_2 (void);
unsigned char DP_RX_Main_Video_Info_Stream_3 (void);

unsigned char DP_TX_Configure_MSA_Stream_1 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format);
unsigned char DP_TX_Configure_MSA_Stream_2 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format);
unsigned char DP_TX_Configure_MSA_Stream_3 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format);
unsigned char DP_TX_Configure_MSA_Stream_4 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format);

/**@brief	This API is used to write a value to the particular bits of a Register.
 *  		Base address of register space is added to the specified address
 * @param 	base_add of the register to be accessed
 * @param 	a_enRegsDefs enum of type FPGARegsDefs
 * @param   a_nPropValue value to be written to the Register
 * @return	Returns the write status
 */
unsigned char DP_RegAccessWrite(unsigned int base_add, FPGARegsDefs a_enRegsDefs , unsigned int a_nPropValue){

	unsigned int address  = (base_add + (a_enRegsDefs >> 16));
	unsigned int width    = (a_enRegsDefs & 0xFF);
	unsigned int bitPos   = ((a_enRegsDefs >> 8) & 0xFF);
	unsigned int regVal   = 0;
	int ret = 0;

	if(width < 32)
	{
		a_nPropValue &= (1<<width)-1;
		ret = reg_32b_read(address, &regVal);
		regVal &= ~(((1<<width)-1) << bitPos);
	}
	regVal |= a_nPropValue << bitPos;
	ret = reg_32b_write(address, regVal);

	return NO_ERROR;
}

/**@brief	This API is used to read value from the particular bits of a Register.
 *  		Base address of register space is added to the specified address
 * @param 	base_add of the register to be accessed
 * @param 	a_enRegsDefs enum of type FPGARegsDefs
 * @param   a_nPropValue a pointer to an unsigned int , return the value read from the specified register .
 * @return	Returns the read status
 */
unsigned char DP_RegAccessRead(unsigned int base_add, FPGARegsDefs a_enRegsDefs , unsigned int *a_nPropValue){

	unsigned int address  = (base_add + (a_enRegsDefs >> 16));
	unsigned int width    = (a_enRegsDefs & 0xFF);
	unsigned int bitPos   = ((a_enRegsDefs >> 8) & 0xFF);
	unsigned int regVal   = 0;
	int ret = 0;

	ret = reg_32b_read(address, &regVal);
	regVal >>= bitPos;
	if(width < 32)
		regVal &= ((1<<width)-1);
	*a_nPropValue = regVal;

	return NO_ERROR;
}

/**@brief	This API is used to configure block 1(32 registers related to video)
 *  		and block 2 (32 registers related to audio), with the value given as input argument.
 * @param 	EDID_reg_val Value to be configured in EDID registers.(All 64 registers)
 * @return 	Returns the write status
 */
unsigned char DP_RX_EDID_Bulk_Config (unsigned int EDID_reg_val){

	unsigned int i = 0;
	for(i = 0 ; i < NUMBER_OF_EDID_REGISTERS ; i++)
	{
		reg_32b_write((RX_EDID_STARTING_ADD + (i* 0x4)), EDID_reg_val);
	}
	return NO_ERROR;
}

/**@brief	This API configures the value to the address of EDID ,  given as input arguments.
 *  		Valid address ranges from 0x100 to 0x1FC(64 registers).
 * @param 	EDID_add EDID address on which value is to be configured (0x100 to 0x1FC)
 * @param 	EDID_reg_val Value to be configured in EDID registers.(All 64 registers)
 * @return 	Returns the write status
 */
unsigned char DP_RX_EDID_Single_Config(unsigned int EDID_add, unsigned int EDID_reg_val) {
	if ((EDID_add >= 0x100) && ((EDID_add - 0x100) % 0x4 == 0) && (EDID_add <= 0x1FC)) {
		reg_32b_write(DP_RX_REG_BASE_ADD + EDID_add, EDID_reg_val);
		return NO_ERROR;
	} else {
		printf("Invalid input address\r\n");
		return ERROR;
	}
}

//Status APIs
/**@brief	This API read Rx Video Stream MSA parameters from RX MSA registers and display them .
 * 			stream number 0 to 3 can be selected.
 * @param 	stream_number stream 0 to 3 to be selected
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Video_Stream_MSA_Info (unsigned int stream_number){

	if (stream_number == 0) {
		return DP_RX_Video_Stream_0_MSA_Info();
	}else if (stream_number == 1) {
		return DP_RX_Video_Stream_1_MSA_Info();
	} else if (stream_number == 2) {
		return DP_RX_Video_Stream_2_MSA_Info();
	}else if (stream_number == 3) {
		return DP_RX_Video_Stream_3_MSA_Info();
	}else{
		printf("Unknown Stream Selected\r\n");
		return ERROR;
	}
}

/**@brief	This API read Rx Video Stream 0 MSA parameters from RX MSA registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Video_Stream_0_MSA_Info (void){
	unsigned int ret ;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MVID_S0, &reg_val);
	if(ret == 0 ){
		printf("MVID_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NVID_S0, &reg_val);
	if(ret == 0 ){
		printf("NVID_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HTOTAL_S0, &reg_val);
	if(ret == 0 ){
		printf("HTOTAL_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VTOTAL_S0, &reg_val);
	if(ret == 0 ){
		printf("VTOTAL_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S0, &reg_val);
	if(ret == 0 ){
		printf("HWIDTH_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S0, &reg_val);
	if(ret == 0 ){
		printf("VHEIGHT_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSTART_S0, &reg_val);
	if(ret == 0 ){
		printf("HSTART_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSTART_S0, &reg_val);
	if(ret == 0 ){
		printf("VSTART_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_WIDTH_S0, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_WIDTH_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_WIDTH_S0, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_WIDTH_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S0, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S0_BPC, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S0_BPC : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT, &reg_val);
	if(ret == 0 ){
		printf("PIX_FORMAT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC1_S0, &reg_val);
	if(ret == 0 ){
		printf("MISC1_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_POLARITY_S0, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_POLARITY_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_POLARITY_S0, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_POLARITY_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_VALID_IN_S0, &reg_val);
	if(ret == 0 ){
		printf("MSA_VALID_IN_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_FORMAT_ERROR_S0, &reg_val);
	if(ret == 0 ){
		printf("MSA_FORMAT_ERROR_S0 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VB_ID_FORMAT_ERROR_S0, &reg_val);
	if(ret == 0 ){
		printf("VB_ID_FORMAT_ERROR_S0 : %u\r\n",reg_val);
	}

	return NO_ERROR;
}


/**@brief	This API read Rx Video Stream 1 MSA parameters from RX MSA registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Video_Stream_1_MSA_Info (void){
	unsigned int ret ;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MVID_S1, &reg_val);
	if(ret == 0 ){
		printf("MVID_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NVID_S1, &reg_val);
	if(ret == 0 ){
		printf("NVID_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HTOTAL_S1, &reg_val);
	if(ret == 0 ){
		printf("HTOTAL_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VTOTAL_S1, &reg_val);
	if(ret == 0 ){
		printf("VTOTAL_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S1, &reg_val);
	if(ret == 0 ){
		printf("HWIDTH_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S1, &reg_val);
	if(ret == 0 ){
		printf("VHEIGHT_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSTART_S1, &reg_val);
	if(ret == 0 ){
		printf("HSTART_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSTART_S1, &reg_val);
	if(ret == 0 ){
		printf("VSTART_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_WIDTH_S1, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_WIDTH_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_WIDTH_S1, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_WIDTH_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S1, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S1_BPC, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S1_BPC : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S1, &reg_val);
	if(ret == 0 ){
		printf("PIX_FORMAT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC1_S1, &reg_val);
	if(ret == 0 ){
		printf("MISC1_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_POLARITY_S1, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_POLARITY_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_POLARITY_S1, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_POLARITY_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_VALID_IN_S1, &reg_val);
	if(ret == 0 ){
		printf("MSA_VALID_IN_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_FORMAT_ERROR_S1, &reg_val);
	if(ret == 0 ){
		printf("MSA_FORMAT_ERROR_S1 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VB_ID_FORMAT_ERROR_S1, &reg_val);
	if(ret == 0 ){
		printf("VB_ID_FORMAT_ERROR_S1 : %u\r\n",reg_val);
	}
	return NO_ERROR;
}


/**@brief	This API read Rx Video Stream 2 MSA parameters from RX MSA registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Video_Stream_2_MSA_Info (void){
	unsigned int ret ;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MVID_S2, &reg_val);
	if(ret == 0 ){
		printf("MVID_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NVID_S2, &reg_val);
	if(ret == 0 ){
		printf("NVID_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HTOTAL_S2, &reg_val);
	if(ret == 0 ){
		printf("HTOTAL_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VTOTAL_S2, &reg_val);
	if(ret == 0 ){
		printf("VTOTAL_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S2, &reg_val);
	if(ret == 0 ){
		printf("HWIDTH_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S2, &reg_val);
	if(ret == 0 ){
		printf("VHEIGHT_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSTART_S2, &reg_val);
	if(ret == 0 ){
		printf("HSTART_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSTART_S2, &reg_val);
	if(ret == 0 ){
		printf("VSTART_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_WIDTH_S2, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_WIDTH_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_WIDTH_S2, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_WIDTH_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S2, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S2_BPC, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S2_BPC : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S2, &reg_val);
	if(ret == 0 ){
		printf("PIX_FORMAT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC1_S2, &reg_val);
	if(ret == 0 ){
		printf("MISC1_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_POLARITY_S2, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_POLARITY_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_POLARITY_S2, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_POLARITY_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_VALID_IN_S2, &reg_val);
	if(ret == 0 ){
		printf("MSA_VALID_IN_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_FORMAT_ERROR_S2, &reg_val);
	if(ret == 0 ){
		printf("MSA_FORMAT_ERROR_S2 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VB_ID_FORMAT_ERROR_S2, &reg_val);
	if(ret == 0 ){
		printf("VB_ID_FORMAT_ERROR_S2 : %u\r\n",reg_val);
	}
	return NO_ERROR;
}

/**@brief	This API read Rx Video Stream 3 MSA parameters from RX MSA registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Video_Stream_3_MSA_Info (void){
	unsigned int ret ;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MVID_S3, &reg_val);
	if(ret == 0 ){
		printf("MVID_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NVID_S3, &reg_val);
	if(ret == 0 ){
		printf("NVID_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HTOTAL_S3, &reg_val);
	if(ret == 0 ){
		printf("HTOTAL_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VTOTAL_S3, &reg_val);
	if(ret == 0 ){
		printf("VTOTAL_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S3, &reg_val);
	if(ret == 0 ){
		printf("HWIDTH_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S3, &reg_val);
	if(ret == 0 ){
		printf("VHEIGHT_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSTART_S3, &reg_val);
	if(ret == 0 ){
		printf("HSTART_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSTART_S3, &reg_val);
	if(ret == 0 ){
		printf("VSTART_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_WIDTH_S3, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_WIDTH_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_WIDTH_S3, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_WIDTH_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S3, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S3_BPC, &reg_val);
	if(ret == 0 ){
		printf("MISC0_S3_BPC : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S3, &reg_val);
	if(ret == 0 ){
		printf("PIX_FORMAT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC1_S3, &reg_val);
	if(ret == 0 ){
		printf("MISC1_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HSYNC_POLARITY_S3, &reg_val);
	if(ret == 0 ){
		printf("HSYNC_POLARITY_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VSYNC_POLARITY_S3, &reg_val);
	if(ret == 0 ){
		printf("VSYNC_POLARITY_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_VALID_IN_S3, &reg_val);
	if(ret == 0 ){
		printf("MSA_VALID_IN_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MSA_FORMAT_ERROR_S3, &reg_val);
	if(ret == 0 ){
		printf("MSA_FORMAT_ERROR_S3 : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VB_ID_FORMAT_ERROR_S3, &reg_val);
	if(ret == 0 ){
		printf("VB_ID_FORMAT_ERROR_S3 : %u\r\n",reg_val);
	}
	return NO_ERROR;
}

/**@brief	This API read Rx Link Sink parameters from RX registers and display them.
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Link_Sink_Status (void){

	unsigned int ret ;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PHY_LANE_RATE, &reg_val);
	if(ret == 0 ){
		printf("RX phy Lane Rate : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NO_OF_PHY_LANES, &reg_val);
	if(ret == 0 ){
		printf("RX number of phy Lanes : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MPCS_READY, &reg_val);
	if(ret == 0 ){
		printf("RX MPCS READY : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_LINK_ERROR, &reg_val);
	if(ret == 0 ){
		printf("RX LINK ERROR : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_TRAINING_DONE, &reg_val);
	if(ret == 0 ){
		printf("RX TRAINING DONE OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_RX_STATE_OUT, &reg_val);
	if(ret == 0 ){
		printf("RX STATE OUT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_ENHANCED_MODE_EN, &reg_val);
	if(ret == 0 ){
		if(reg_val == 0){
			printf("RX Framing Mode : Normal\r\n",reg_val);
		}else if (reg_val == 1){
			printf("RX Framing Mode : Enhance\r\n",reg_val);
		}
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_STREAM_COUNT_INT, &reg_val);
	if(ret == 0 ){
		printf("RX VIDEO STREAM COUNT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_RESOLUTION_LOCKED, &reg_val);
	if(ret == 0 ){
		printf("RX RESOLUTION LOCKED (S0) OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_RESOLUTION_LOCKED_S1, &reg_val);
	if(ret == 0 ){
		printf("RX RESOLUTION LOCKED (S1) OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_RESOLUTION_LOCKED_S2, &reg_val);
	if(ret == 0 ){
		printf("RX RESOLUTION LOCKED (S2) OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_RESOLUTION_LOCKED_S3, &reg_val);
	if(ret == 0 ){
		printf("RX RESOLUTION LOCKED (S3) OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_EDID_CHECK_CAL_DONE, &reg_val);
	if(ret == 0 ){
		printf("RX EDID CHECKSUM CALCULATION DONE OR NOT : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S0, &reg_val);
	if(ret == 0 ){
		if(reg_val == 0)
		{
			printf("RX INTERLACE SUPPORT S0 : Progressive\r\n");
		}else if(reg_val == 1)
		{
			printf("RX INTERLACE SUPPORT S0 : Interlaced\r\n");
		}
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S1, &reg_val);
	if(ret == 0 ){
		if(reg_val == 0)
		{
			printf("RX INTERLACE SUPPORT S1 : Progressive\r\n");
		}else if(reg_val == 1)
		{
			printf("RX INTERLACE SUPPORT S1 : Interlaced\r\n");
		}
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S2, &reg_val);
	if(ret == 0 ){
		if(reg_val == 0)
		{
			printf("RX INTERLACE SUPPORT S2 : Progressive\r\n");
		}else if(reg_val == 1)
		{
			printf("RX INTERLACE SUPPORT S2 : Interlaced\r\n");
		}
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S3, &reg_val);
	if(ret == 0 ){
		if(reg_val == 0)
		{
			printf("RX INTERLACE SUPPORT S3 : Progressive\r\n");
		}else if(reg_val == 1)
		{
			printf("RX INTERLACE SUPPORT S3 : Interlaced\r\n");
		}
	}
	return NO_ERROR;
}

/**@brief	This API polls RX training bit and show if the training is done .
 *  		If training is not done until timeout then displays training unsuccessful.
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Get_Training_Status (void){

	unsigned char ret;
	unsigned int train_bit;
	unsigned int count = 0;

	while (count < 30){ //15 sec
		delayMS(1000);
		ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_TRAINING_DONE, &train_bit);
		if(ret == 0){
			printf("Train bit read: %u\r\n",train_bit);
		}

		if(ret == 0 && train_bit == 0x1){
			break;
		}
		delayMS(1);
		count++;
	}
	if(count == 30) {
		printf("Upstream training is unsuccessful\r\n");
		return ERROR;
	}

	return NO_ERROR;
}

/**@brief	This API reads RX main video info stream  parameters and display them .
 * 			stream number 0 to 3 can be selected.
 * @param 	stream_number stream 0 to 3 to be selected
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Main_Video_Info_Stream (unsigned int stream_number){

	if (stream_number == 0) {
		return DP_RX_Main_Video_Info_Stream_0();
	}else if (stream_number == 1) {
		return DP_RX_Main_Video_Info_Stream_1();
	} else if (stream_number == 2) {
		return DP_RX_Main_Video_Info_Stream_2();
	}else if (stream_number == 3) {
		return DP_RX_Main_Video_Info_Stream_3();
	}else{
		printf("Unknown Stream Selected\r\n");
		return ERROR;
	}

}

/**@brief	This API reads RX main video info stream 0 parameters and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Main_Video_Info_Stream_0 (void){

	unsigned int ret;
	unsigned int bpc;
	unsigned int Color_Type;
	unsigned int FPS_CAL;
	unsigned int FPS_CAL_Actual;
	unsigned int scan_info;
	unsigned int pixel_format;
	unsigned int Vheight_Actual;
	unsigned int Hwidth;
	unsigned int Vheight;

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S0, &Hwidth);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Hwidth read: %u\r\n",Hwidth);
#endif
	}
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S0, &Vheight);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Vheight read: %u\r\n",Vheight);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S0_BPC, &bpc);
	if (ret==0){
#if REG_READ_DEBUG
		printf("bpc read: %u\r\n",bpc);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT, &Color_Type);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Color_Type read: %u\r\n",Color_Type);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S0, &scan_info);
	if (ret==0){
#if REG_READ_DEBUG
		printf("scan_info read: %u\r\n",scan_info);
#endif
	}

	if(scan_info == 0)
	{
		Vheight_Actual = Vheight;
		FPS_CAL_Actual = FPS_CAL;
	}else if(scan_info == 1)
	{
		Vheight_Actual = Vheight*2;
		FPS_CAL_Actual = FPS_CAL/2;
	}

	printf("Resolution   : %ux%u\r\n", Hwidth , Vheight_Actual);

	//Scaning
	if(scan_info == 0)
	{
		printf("Scan Type    : Progressive\r\n");
	}else if(scan_info == 1)
	{
		printf("Scan Type    : Interlaced\r\n");
	}

	//Color
	if(Color_Type == 0)
	{
		printf("Pixel Format : RGB888\r\n");
	}else if(Color_Type == 1)
	{
		printf("Pixel Format : YCbCr422\r\n");
	}else if(Color_Type == 2)
	{
		printf("Pixel Format : YCbCr444\r\n");
	}

	//BPC

	if(bpc == 0)
	{
		printf("BPC          : 6\r\n");
	}else if(bpc == 1)
	{
		printf("BPC          : 8\r\n");
	}
	else if(bpc == 2)
	{
		printf("BPC          : 10\r\n");
	}else if(bpc == 3)
	{
		printf("BPC          : 12\r\n");
	}else if(bpc == 4)
	{
		printf("BPC          : 16\r\n");
	}
	return NO_ERROR;
}

/**@brief	This API reads RX main video info stream 1 parameters and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Main_Video_Info_Stream_1 (void){

	unsigned int ret;
	unsigned int bpc;
	unsigned int Color_Type;
	unsigned int FPS_CAL;
	unsigned int FPS_CAL_Actual;
	unsigned int scan_info;
	unsigned int pixel_format;
	unsigned int Vheight_Actual;
	unsigned int Hwidth;
	unsigned int Vheight;

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S1, &Hwidth);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Hwidth read: %u\r\n",Hwidth);
#endif
	}
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S1, &Vheight);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Vheight read: %u\r\n",Vheight);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S1_BPC, &bpc);
	if (ret==0){
#if REG_READ_DEBUG
		printf("bpc read: %u\r\n",bpc);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S1, &Color_Type);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Color_Type read: %u\r\n",Color_Type);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S1, &scan_info);
	if (ret==0){
#if REG_READ_DEBUG
		printf("scan_info read: %u\r\n",scan_info);
#endif
	}

	if(scan_info == 0)
	{
		Vheight_Actual = Vheight;
		FPS_CAL_Actual = FPS_CAL;
	}else if(scan_info == 1)
	{
		Vheight_Actual = Vheight*2;
		FPS_CAL_Actual = FPS_CAL/2;
	}

	printf("Resolution   : %ux%u\r\n", Hwidth , Vheight_Actual);

	//Scaning
	if(scan_info == 0)
	{
		printf("Scan Type    : Progressive\r\n");
	}else if(scan_info == 1)
	{
		printf("Scan Type    : Interlaced\r\n");
	}

	//Color
	if(Color_Type == 0)
	{
		printf("Pixel Format : RGB888\r\n");
	}else if(Color_Type == 1)
	{
		printf("Pixel Format : YCbCr422\r\n");
	}else if(Color_Type == 2)
	{
		printf("Pixel Format : YCbCr444\r\n");
	}

	//BPC

	if(bpc == 0)
	{
		printf("BPC          : 6\r\n");
	}else if(bpc == 1)
	{
		printf("BPC          : 8\r\n");
	}
	else if(bpc == 2)
	{
		printf("BPC          : 10\r\n");
	}else if(bpc == 3)
	{
		printf("BPC          : 12\r\n");
	}else if(bpc == 4)
	{
		printf("BPC          : 16\r\n");
	}

	return NO_ERROR;
}

/**@brief	This API reads RX main video info stream 2 parameters and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Main_Video_Info_Stream_2 (void){
	unsigned int ret;
	unsigned int bpc;
	unsigned int Color_Type;
	unsigned int FPS_CAL;
	unsigned int FPS_CAL_Actual;
	unsigned int scan_info;
	unsigned int pixel_format;
	unsigned int Vheight_Actual;
	unsigned int Hwidth;
	unsigned int Vheight;

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S2, &Hwidth);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Hwidth read: %u\r\n",Hwidth);
#endif
	}
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S2, &Vheight);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Vheight read: %u\r\n",Vheight);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S2_BPC, &bpc);
	if (ret==0){
#if REG_READ_DEBUG
		printf("bpc read: %u\r\n",bpc);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S2, &Color_Type);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Color_Type read: %u\r\n",Color_Type);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S2, &scan_info);
	if (ret==0){
#if REG_READ_DEBUG
		printf("scan_info read: %u\r\n",scan_info);
#endif
	}

	if(scan_info == 0)
	{
		Vheight_Actual = Vheight;
		FPS_CAL_Actual = FPS_CAL;
	}else if(scan_info == 1)
	{
		Vheight_Actual = Vheight*2;
		FPS_CAL_Actual = FPS_CAL/2;
	}

	printf("Resolution   : %ux%u\r\n", Hwidth , Vheight_Actual);

	//Scaning
	if(scan_info == 0)
	{
		printf("Scan Type    : Progressive\r\n");
	}else if(scan_info == 1)
	{
		printf("Scan Type    : Interlaced\r\n");
	}

	//Color
	if(Color_Type == 0)
	{
		printf("Pixel Format : RGB888\r\n");
	}else if(Color_Type == 1)
	{
		printf("Pixel Format : YCbCr422\r\n");
	}else if(Color_Type == 2)
	{
		printf("Pixel Format : YCbCr444\r\n");
	}

	//BPC
	if(bpc == 0)
	{
		printf("BPC          : 6\r\n");
	}else if(bpc == 1)
	{
		printf("BPC          : 8\r\n");
	}
	else if(bpc == 2)
	{
		printf("BPC          : 10\r\n");
	}else if(bpc == 3)
	{
		printf("BPC          : 12\r\n");
	}else if(bpc == 4)
	{
		printf("BPC          : 16\r\n");
	}
	return NO_ERROR;
}

/**@brief	This API reads RX main video info stream 3 parameters and display them .
 * @param 	void
 * @return 	Returns the read status
 */
unsigned char DP_RX_Main_Video_Info_Stream_3 (void){
	unsigned int ret;
	unsigned int bpc;
	unsigned int Color_Type;
	unsigned int FPS_CAL;
	unsigned int FPS_CAL_Actual;
	unsigned int scan_info;
	unsigned int pixel_format;
	unsigned int Vheight_Actual;
	unsigned int Hwidth;
	unsigned int Vheight;

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_HWIDTH_S3, &Hwidth);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Hwidth read: %u\r\n",Hwidth);
#endif
	}
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_VHEIGHT_S3, &Vheight);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Vheight read: %u\r\n",Vheight);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MISC0_S3_BPC, &bpc);
	if (ret==0){
#if REG_READ_DEBUG
		printf("bpc read: %u\r\n",bpc);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_PIX_FORMAT_S3, &Color_Type);
	if (ret==0){
#if REG_READ_DEBUG
		printf("Color_Type read: %u\r\n",Color_Type);
#endif
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_INTERLACE_SUPPORT_S3, &scan_info);
	if (ret==0){
#if REG_READ_DEBUG
		printf("scan_info read: %u\r\n",scan_info);
#endif
	}

	if(scan_info == 0)
	{
		Vheight_Actual = Vheight;
		FPS_CAL_Actual = FPS_CAL;
	}else if(scan_info == 1)
	{
		Vheight_Actual = Vheight*2;
		FPS_CAL_Actual = FPS_CAL/2;
	}

	printf("Resolution   : %ux%u\r\n", Hwidth , Vheight_Actual);

	//Scaning
	if(scan_info == 0)
	{
		printf("Scan Type    : Progressive\r\n");
	}else if(scan_info == 1)
	{
		printf("Scan Type    : Interlaced\r\n");
	}

	//Color
	if(Color_Type == 0)
	{
		printf("Pixel Format : RGB888\r\n");
	}else if(Color_Type == 1)
	{
		printf("Pixel Format : YCbCr422\r\n");
	}else if(Color_Type == 2)
	{
		printf("Pixel Format : YCbCr444\r\n");
	}

	//BPC
	if(bpc == 0)
	{
		printf("BPC          : 6\r\n");
	}else if(bpc == 1)
	{
		printf("BPC          : 8\r\n");
	}
	else if(bpc == 2)
	{
		printf("BPC          : 10\r\n");
	}else if(bpc == 3)
	{
		printf("BPC          : 12\r\n");
	}else if(bpc == 4)
	{
		printf("BPC          : 16\r\n");
	}
	return NO_ERROR;
}

/**@brief	This API reads RX audio time stamp parameters and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Audio_Time_Stamp (void){

	unsigned int ret;
	unsigned int reg_val;
	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_MAUD, &reg_val);
	if (ret==0){
		printf("RX MAUD : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_NAUD, &reg_val);
	if (ret==0){
		printf("RX NAUD : %u\r\n",reg_val);
	}

	return NO_ERROR;
}

/**@brief	This API reads RX audio info parameters and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_RX_Audio_Info (void){

	unsigned int ret;
	unsigned int reg_val;

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_CHANNEL_COUNT, &reg_val);
	if (ret==0){
		printf("RX audio_channel_count : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_FORMAT_TYPE, &reg_val);
	if (ret==0){
		printf("RX audio_format_type : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_SAMPLE_SIZE, &reg_val);
	if (ret==0){
		printf("RX audio_sample_size : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_SAMPLE_FREQUENCY, &reg_val);
	if (ret==0){
		printf("RX audio_sample_frequency : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_STREAM_TYPE, &reg_val);
	if (ret==0){
		printf("RX audio_stream_type : %u\r\n",reg_val);
	}

	ret = DP_RegAccessRead(DP_RX_REG_BASE_ADD , DP_RX_AUDIO_SPEAKER_MAPPING, &reg_val);
	if (ret==0){
		printf("RX audio_speaker_mapping : %u\r\n",reg_val);
	}

	return NO_ERROR;
}

//Tx

/**@brief	This API  reads TX CD capabilities from the TX registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_CD_Capabilities (void){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int edid_H_visible;
	unsigned int edid_V_visible ;
	unsigned int count = 0;


	while(count < 15000) {
		printf("Sink is no detected\r\n");
		ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_HPD_FROM_SINK, &reg_val);
		if(ret == 0 && reg_val == 0x1) {
			printf("Sink is detected\r\n");
			break;
		}
		delayMS(1); // wait for 1ms
		count++;
		if(count == 15000) {
			printf("Sink is not connected\r\n");
			printf("Trying to detect the sink again\r\n");
			return ERROR;
		}
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_TX_STATE, &reg_val);
	if(!(ret == 0 && reg_val == 0x2)) {
		//printf("TX state not 2\r\n");
		return ERROR;
	}

	//max_link_rate
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_MAX_LAN_RATE , &reg_val);
	if (ret == 0) {
		printf("Max link rate: 0x%02X\r\n" , reg_val);
	}

	//max_lane_count
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_MAX_LAN_COUNT , &reg_val);
	if (ret == 0) {
		printf("Max lane count : 0x%X\r\n" , reg_val);
	}

	//edid_H_visible
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_EDID_H_VISIBLE , &edid_H_visible);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("edid_H_visible : %u\r\n" , edid_H_visible);
#endif
	}

	//edid_V_visible

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_EDID_V_VISIBLE , &edid_V_visible);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("edid_H_visible : %u\r\n" , edid_H_visible);
#endif
	}

	printf("Recommended resolution: %u x %u\r\n" , edid_H_visible , edid_V_visible  );

	//enhance_frame_cap
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_ENHANCE_MODE , &reg_val);
	if (ret == 0) {
		printf("DP_TX_ENHANCE_MODE or not : %u\r\n" , reg_val);
	}

	//tsp3_support
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_TPS3_SUPPORTED , &reg_val);
	if (ret == 0) {
		printf("TPS3_SUPPORTED or not : %u\r\n" , reg_val);
	}
	//tsp4_support
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_TPS4_SUPPORTED , &reg_val);
	if (ret == 0) {
		printf("TPS4_SUPPORTED or not : %u\r\n" , reg_val);
	}
	//aux_link_training
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_NO_AUX_TRANS_LINK_TRAIN , &reg_val);
	if (ret == 0) {
		printf("No aux transactions supported : %u\r\n" , reg_val);
	}

	return NO_ERROR;
}

/**@brief	This API  reads TX EDID capabilities from the TX registers and display them .
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_EDID_Capabilities (void){

	unsigned int ret;
	unsigned int address;
	unsigned int regVal;
	unsigned int edit_reg_sum = 0x0;
	unsigned int i;

	printf("EDID VALIDATED\r\n");
	for(i = 0 ; i < 256 ; i++)
	{
		printf("EDID non done VALIDATED\r\n");
	    ret = DP_RegAccessRead  (DP_TX_REG_BASE_ADD , DP_TX_EDID_DATA  , &regVal);
		edit_reg_sum +=  (regVal & 0x000000FF);
	}
	if((edit_reg_sum & 0x000000FF) == 0x0){
		printf("EDID VALIDATED\r\n");
	}else{
		printf("EDID Checksum Error\r\n");
	}

	return NO_ERROR;
}

/**@brief	This API polls Training bit of TX and if it is 1 then displays Training done
 * 			and show lane rate and lane count value on which training is done
 * 			otherwise read ts_transmit value and show status accordingly.
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Training_Status (void){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int count = 0;
	unsigned int train_bit;
	while(1){ //break is already there for 20 cycles so no need to remove this while(1) in driver API
		count = 0 ;
		while(count < 20000) {

			printf("Training is not done\r\n");
			ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_TRAIN_BIT, &train_bit);

			if(ret == 0 && train_bit == 0x1) {
				printf("Training is done\r\n");
				printf("Clock Recovery Successful\r\n");
				printf("Channel Equalization Successful\r\n");
				printf("Symbol Locked\r\n");
				break;
			}
			delayMS(1); // wait for 1ms
			count++;
			if(count == 20000) {
				printf("Training Unsuccessful\r\n");
				ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_TS_TRANSMIT, &reg_val);
				if(ret == 0){
					if(reg_val > 1){
						printf("Clock Recovery Successful\r\n");
						printf("Channel Equalization Failed\r\n");
						printf("Symbol Unlocked\r\n");
						printf("Retraining is in process\r\n");
					}else if (reg_val == 1){
						printf("Clock Recovery Failed\r\n");
						printf("Channel Equalization Failed\r\n");
						printf("Symbol Unlocked\r\n");
						printf("Retraining is in process\r\n");
					}
					else if (reg_val == 0){
						printf("Training Failed\r\n");
					}
				}
			}
		}
		if(train_bit == 0x1 || count == 20000 * 20)
		{
			break;
		}
	}
	return NO_ERROR;
}


/**@brief	This API configure TX Misc parameters of DP TX ,
 	 	 	 according to the resolution given as input
 * @param 	pixel_format  0 for RGB ,  1 for YCBCR444, 2 for YCBCR422 and 3 for RAW.
 * @param 	bpc.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MISC(unsigned int stream, unsigned int bpc, unsigned int pixel_format){
	unsigned int ret;
    unsigned int misc;
	  if(pixel_format == 0){
	     if(bpc == 6){
	    	 misc = 0x1;
	     } else if(bpc == 8){
	        misc = 0x21;
	     } else if(bpc == 10){
	        misc = 0x41;
	     } else if(bpc == 12){
	        misc = 0x61;
	     } else if(bpc == 16){
	        misc = 0x81;
	     } else{
	        misc = 0;
		 }
	  } else if(pixel_format == 1){
	     if(bpc == 8){
	        misc = 45;
	     } else if(bpc == 10){
	        misc = 77;
	     } else if(bpc == 12){
	        misc = 109;
	     } else if(bpc == 16){
	        misc = 141;
	     } else{
	        misc = 0;
	     }
	  } else if(pixel_format == 2){
	     if(bpc == 8){
	        misc = 59;
	     } else if(bpc == 10){
	        misc = 91;
	     } else if(bpc == 12){
	        misc = 123;
	     } else if(bpc == 16){
	        misc = 155;
	     } else{
	        misc = 0;
		 }
	  } else if(pixel_format == 3){
	     if(bpc == 6){
	        misc = 35;
	     } else if(bpc == 7){
	        misc = 67;
	     } else if(bpc == 8){
	        misc = 99;
	     } else if(bpc == 10){
	        misc = 131;
	     } else if(bpc == 12){
	        misc = 163;
	     } else if(bpc == 14){
	        misc = 195;
	     } else if(bpc == 16){
	        misc = 227;
	     } else{
	        misc = 0;
		 }
		}else {
			misc =0;
		}
if(stream ==1){
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC0 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC0 register written with value: 0x%x\r\n" ,misc);
    #endif
    	}
    	  if(pixel_format == 3){
    		misc =128;
    	  }else {
    		misc =0;
    	  }
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC1 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC1 register written with value: 0x%x\r\n",misc);
    #endif
    	}
}else if (stream == 2){
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC0_2 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC0_2 register written with value: 0x%x\r\n" ,misc);
    #endif
    	}
    	  if(pixel_format == 3){
    		misc =128;
    	  }else {
    		misc =0;
    	  }
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC1_2 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC1_2 register written with value: 0x%x\r\n",misc);
    #endif
    	}
}else if (stream == 3){
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC0_3 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC0_3 register written with value: 0x%x\r\n" ,misc);
    #endif
    	}
    	  if(pixel_format == 3){
    		misc =128;
    	  }else {
    		misc =0;
    	  }
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC1_3 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC1_3 register written with value: 0x%x\r\n",misc);
    #endif
    	}
}else if (stream == 4){
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC0_4 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC0_4 register written with value: 0x%x\r\n" ,misc);
    #endif
    	}
    	  if(pixel_format == 3){
    		misc =128;
    	  }else {
    		misc =0;
    	  }
    	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MISC1_4 , misc);
    	if (ret ==0) {
    #if REG_WRITE_DEBUG
    		printf("DP_TX_MISC1_4 register written with value: 0x%x\r\n",misc);
    #endif
    	}
}
	return NO_ERROR;
}
/**@brief	This API configure TX MSA parameters of DP TX and VTG registers,
 	 	 	 according to the resolution given as input
 * @param 	resolution  0 for 720p ,  1 for 1080p and 2 for 4k.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA (unsigned int resolution, unsigned int bpc, unsigned int pixel_format){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int fps = 60;
	unsigned int mvid_val;
	unsigned int pll_refclk_lock;
	unsigned int pll_vidclk_lock;
	unsigned int Tu_size_in_symbol_cnt = 64;
	double avg_valid_symbols_per_TU;
	double peak_stream_bandwidth;
	double val1;
	double val2;
	unsigned int remainder1;
	unsigned int Max_lane_rate;
	unsigned int Max_lane_count;
	unsigned int bpp;
	unsigned int ts_int;
	unsigned int ts_frac;
	unsigned int ppc;
	unsigned int cnt=4;

	// MISC0 and MISC1 allocation
	DP_TX_Configure_MISC(1,bpc,pixel_format);
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW, &Max_lane_rate);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_rate read :  0x%02X\r\n" , Max_lane_rate);
#endif
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT, &Max_lane_count);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_count read :  0x%x\r\n" , Max_lane_count);
#endif
	}

	if((pixel_format == 0)||(pixel_format==1)){// RGB/YCbCr444
		bpp = 3*bpc;
	}else if(pixel_format == 2){// YCbCr422
		bpp = 2*bpc;
	}else if(pixel_format == 3){//RAW
		bpp = 1*bpc;
	}
	// resolution 1280x720p
	if (resolution == 0)
	{
		mvid_val = (((1650LL*750LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 1650);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 1650\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 750);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 750\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 1280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 1280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 720);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 720\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 330);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 330\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 25);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 25\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 40);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 40\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 370);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 30);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 30\r\n");
#endif
		}

		    peak_stream_bandwidth = bpp * ((1650LL*750LL)*fps);
	}
	else if(resolution == 1){
		// resolution 1920x1080p

		mvid_val = (((2200LL*1125LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 2200);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 2200\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 1125);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 1125\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 1920);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 1920\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 1080);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 1080\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 192);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 192\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 41);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 41\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 44);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 44\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 45);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 45\r\n");
#endif
		}

	    peak_stream_bandwidth = bpp * ((2200LL*1125LL)*fps);

	}
	else
	{
		// resolution 3840x2160p

		mvid_val = (((4400LL*2250LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" ,mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 4400);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 4400\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 2250);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 2250\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 3840);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 3840\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 2160);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 2160\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 384);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 384\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 82);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 82\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 88);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 88\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 10);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 10\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 560);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 90);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 30\r\n");
#endif
		}

			    peak_stream_bandwidth = bpp * ((4400LL*2250LL)*fps);
	}
        	val2 = 8.0 * Max_lane_count * Max_lane_rate * 27LL *1000000LL;
        	avg_valid_symbols_per_TU = (((peak_stream_bandwidth) / (val2)) * 64);
        	ts_int  = (int)(avg_valid_symbols_per_TU);

        	val1    = (avg_valid_symbols_per_TU)-(int)(avg_valid_symbols_per_TU);
            cnt     = 4;
            ts_frac = 0;
        while (cnt >0) {
                	val1    = val1*2;
                	ts_frac = ts_frac + ((int)(val1))*(1<<(cnt-1));
                	val1    = val1 -(int)(val1);
                    cnt     -=1 ;
                    if(cnt==0){
                    	ts_frac +=1;
                    	if(ts_frac==16){
                    		ts_frac=0;
                    		ts_int+=1;
                    	}
                    }
                };
    ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_INT , ts_int);
    if (ret ==0) {
#if REG_WRITE_DEBUG
    printf("DP_TX_TS_INT register written with value: %u\r\n", ts_int);
#endif
    }

    ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_FRAC ,ts_frac);
    if (ret ==0) {
#if REG_WRITE_DEBUG
    printf("DP_TX_TS_FRAC register written with value: %u\r\n", ts_frac);
#endif
    }
	return NO_ERROR;
}

/**@brief	This API configures speaker mapping , channel count ,
 * 			sampling frequency , sample bit size parameters in TX registers.
 * @param 	audioConfig  AudioConfig structure (parameters to be configured)
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Enable_Audio(const AudioConfig *audioConfig){

	unsigned int ret;
	unsigned int reg_val;

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_SPEAKER_MAPPING, audioConfig -> speaker_mapping);
	if (ret==0){
		printf("TX speaker_mapping configured : %u\r\n",audioConfig -> speaker_mapping);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_AUDIO_CHANNEL_COUNT, audioConfig -> channel_count);
	if (ret==0){
		printf("TX channel_count configured : %u\r\n",audioConfig -> channel_count);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_AUDIO_SAMPLE_SIZE, audioConfig -> sampling_frequency);
	if (ret==0){
		printf("TX sampling_frequency configured : %u\r\n",audioConfig -> sampling_frequency);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_AUDIO_SAMPLING_FREQ, audioConfig -> sample_bit_size);
	if (ret==0){
		printf("TX sample_bit_size configured : %u\r\n",audioConfig -> sample_bit_size);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MAUD,audioConfig ->  maud);
	if (ret==0){
		printf("TX maud configured : %u\r\n",audioConfig -> maud);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NAUD, audioConfig -> naud);
	if (ret==0){
		printf("TX naud configured : %u\r\n",audioConfig -> naud);
	}

	return NO_ERROR;

}

/**@brief	This API set lane valid to 1 to enable and  0 to disable the Video on sink device .
 * @param 	En 1 for Enable ,  0 for Disable.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Enable_Disable_Main_Stream(unsigned int En){

	unsigned int ret;
	unsigned int reg_val;
	if (En == 1) {
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_LANE_VALID, 1);
		if (ret == 0) {
			printf("Video Enabled \r\n");
#if REG_WRITE_DEBUG
			printf("DP_TX_LANE_VALID bit set to 1\r\n");
#endif
		}
	} else if(En == 0) {
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_LANE_VALID, 0);
		if (ret == 0) {
#if REG_WRITE_DEBUG
			printf("DP LANE VALID set to 0\r\n");
#endif
		}
	}else{
		printf("Invalid Input Argument\r\n");
	}


	return NO_ERROR;
}

/**@brief	This API reads Frame Error Status , Pixel Count and Line Count from VTG and display the values.
 * @param 	void
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Resolution_Lock(void){

	unsigned int ret;
	unsigned int reg_val;
	return NO_ERROR;
}

/**@brief	This API  enables or disables  Enhance framing mode ,
 * 			configure link rate , lane count , voltage swing and preamphasis to the TX register.
 * @param 	edpConfig EDPConfig structure (parameters to be configured)
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_EDP_Fast_Link(const EDPConfig *edpConfig){

	unsigned int ret;
	unsigned int reg_val;

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW , edpConfig->lane_rate);
	if (ret == 0) {
		if(edpConfig -> lane_rate == 0x06){
			printf("Max_lane_rate read : 1.62 Gbps(RBR)\r\n" );
		}else if(edpConfig -> lane_rate == 0x0A){
			printf("Max_lane_rate read : 2.7 Gbps(HBR1)\r\n" );
		}else if(edpConfig -> lane_rate == 0x14){
			printf("Max_lane_rate read : 5.4 Gbps(HBR2)\r\n" );
		}else if(edpConfig -> lane_rate == 0x1E){
			printf("RX - Max_lane_rate: 8.1 Gbps(HBR3)\r\n" );
		}else{
			printf("Max_lane_rate read : 0x%02X\r\n" , edpConfig -> lane_rate);
		}
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT , edpConfig -> lane_count);
	if (ret == 0) {
		printf("Lane count is configured : 0x%X\r\n" , edpConfig -> lane_count);
	}

	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_ENHANCED_MODE_EN , edpConfig -> enhanced_mode_en);
	if (ret == 0) {
		printf("Emhanced Framing Mode is configured : %u\r\n" , edpConfig ->  enhanced_mode_en);
	}

	//TODO
	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_RX_AUDIO_CHANNEL_COUNT, edpConfig ->  voltage_swing);
	if (ret==0){
		printf("TX voltage swing configured : %u\r\n", edpConfig -> voltage_swing);
	}

	//TODO
	ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_RX_AUDIO_CHANNEL_COUNT, edpConfig ->  preamphasis);
	if (ret==0){
		printf("TX preamphasis configured : %u\r\n", edpConfig -> preamphasis);
	}

	return NO_ERROR;
}

/**@brief	This API  configures TX Stream MSA parameters.(Stream 1 to 4 to be selected)
 * @param 	stream_number 1 to 4 to be selected
 * @param 	resolution 0 for 720p , 1 for 1080p and 2 for 4k.
 * @param	pixel_format to calculate bpp.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA_Stream (unsigned int stream_number , unsigned int resolution , unsigned int bpc , unsigned int pixel_format){

	if (stream_number == 1) {
		return DP_TX_Configure_MSA_Stream_1(resolution, bpc, pixel_format);
	}else if (stream_number == 2) {
		return DP_TX_Configure_MSA_Stream_2(resolution, bpc, pixel_format);
	} else if (stream_number == 3) {
		return DP_TX_Configure_MSA_Stream_3(resolution, bpc, pixel_format);
	}else if (stream_number == 4) {
		return DP_TX_Configure_MSA_Stream_4(resolution, bpc, pixel_format);
	}else{
		printf("Unknown Stream Selected\r\n");
		return ERROR;
	}
}

/**@brief	This API  configures TX Stream 1 MSA parameters.
 * @param 	resolution 0 for 720p , 1 for 1080p and 2 for 4k.
 * @param	pixel_format to calculate bpp.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA_Stream_1 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format )
{

	unsigned int ret;
	unsigned int reg_val;
	unsigned int fps = 60;
	unsigned int mvid_val;
	unsigned int pll_refclk_lock;
	unsigned int pll_vidclk_lock;
	unsigned int misc0;
	unsigned int Max_lane_rate;
	unsigned int Max_lane_count;
	unsigned int ppc;
	unsigned int bpp;
	unsigned int cnt=4;

	double peak_stream_bandwidth;
	double val1;
	double val2;
	double avg_valid_symbols_per_TU;
	double PBN;
	unsigned int Stream_ts_count;
	unsigned int ts_int;
	unsigned int ts_frac;


	// MISC0 and MISC1 allocation
	DP_TX_Configure_MISC(1,bpc,pixel_format);
ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW, &Max_lane_rate);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_rate read :  0x%02X\r\n" , Max_lane_rate);
#endif
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT, &Max_lane_count);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_count read :  0x%x\r\n" , Max_lane_count);
#endif
	}

	if((pixel_format == 0)||(pixel_format==1)){// RGB/YCbCr444
		bpp = 3*bpc;
	}else if(pixel_format == 2){// YCbCr422
		bpp = 2*bpc;
	}else if(pixel_format == 3){//RAW
		bpp = 1*bpc;
	}

	// resolution 1280x720p
	if (resolution == 0)
	{

		peak_stream_bandwidth = bpp*((1650LL*750LL)*fps);

		mvid_val = (((1650LL*750LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 1650);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 1650\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 750);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 750\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 1280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 1280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 720);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 720\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 330);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 330\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 25);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 25\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 40);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 40\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 370);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 30);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 30\r\n");
#endif
		}
	}
	else if(resolution == 1){
		// resolution 1920x1080p

		peak_stream_bandwidth = bpp*((2200LL*1125LL)*fps);

		mvid_val = (((2200LL*1125LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 2200);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 2200\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 1125);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 1125\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 1920);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 1920\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 1080);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 1080\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 192);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 192\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 41);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 41\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 44);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 44\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}


		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 45);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 45\r\n");
#endif
		}
	}
	else
	{
		// resolution 3840x2160p

		peak_stream_bandwidth = bpp*((4400LL*2250LL)*fps);


		mvid_val = (((4400LL*2250LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID register written with value: %u\r\n" ,mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL , 4400);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL register written with value: 4400\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL , 2250);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL register written with value: 2250\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH , 3840);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH register written with value: 3840\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT , 2160);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT register written with value: 2160\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART , 384);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART register written with value: 384\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART , 82);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART register written with value: 82\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH , 88);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH register written with value: 88\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH , 10);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH register written with value: 10\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK , 560);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK , 90);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK register written with value: 30\r\n");
#endif
		}
	}


         	val2 = 8.0 * Max_lane_count * Max_lane_rate * 27LL *1000000LL;
        	avg_valid_symbols_per_TU = (((peak_stream_bandwidth) / (val2)) * 64);
        	ts_int  = (int)(avg_valid_symbols_per_TU);
            Stream_ts_count = (ceil)(avg_valid_symbols_per_TU);

        	val1    = (avg_valid_symbols_per_TU)-(int)(avg_valid_symbols_per_TU);
            cnt     = 4;
            ts_frac = 0;
        while (cnt >0) {
                	val1    = val1*2;
                	ts_frac = ts_frac + ((int)(val1))*(1<<(cnt-1));
                	val1    = val1 -(int)(val1);
                    cnt     -=1 ;
                    if(cnt==0){
                    	ts_frac +=1;
                    	if(ts_frac==16){
                    		ts_frac=0;
                    		ts_int+=1;
                    	}
                    }
                };


	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_INT , ts_int);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_INT register written with value: %u\r\n", ts_int);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_FRAC , ts_frac);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_FRAC register written with value: %u\r\n", ts_frac);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_STREAM1_TS_COUNT , (int)Stream_ts_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_STREAM1_TS_COUNT register written with value: %u\r\n", (int)Stream_ts_count);
#endif
	}

	return NO_ERROR;
}

/**@brief	This API  configures TX Stream 2 MSA parameters.
 * @param 	resolution 0 for 720p , 1 for 1080p and 2 for 4k.
 * @param	pixel_format to calculate bpp.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA_Stream_2 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int fps = 60;
	unsigned int mvid_val;
	unsigned int pll_refclk_lock;
	unsigned int pll_vidclk_lock;
	unsigned int misc0;
	unsigned int Max_lane_rate;
	unsigned int Max_lane_count;
	unsigned int ppc;
	unsigned int bpp;
	unsigned int cnt=4;

	double peak_stream_bandwidth;
	double PBN;
	double val1;
	double val2;
	double avg_valid_symbols_per_TU;
	unsigned int Stream_ts_count;
	unsigned int ts_int;
	unsigned int ts_frac;

	// MISC0 and MISC1 allocation
	DP_TX_Configure_MISC(2,bpc,pixel_format);
	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW, &Max_lane_rate);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_rate read :  0x%02X\r\n" , Max_lane_rate);
#endif
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT, &Max_lane_count);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_count read :  0x%x\r\n" , Max_lane_count);
#endif
	}

	if((pixel_format == 0)||(pixel_format==1)){// RGB/YCbCr444
		bpp = 3*bpc;
	}else if(pixel_format == 2){// YCbCr422
		bpp = 2*bpc;
	}else if(pixel_format == 3){//RAW
		bpp = 1*bpc;
	}
	// resolution 1280x720p
	if (resolution == 0)
	{

		peak_stream_bandwidth = bpp*((1650LL*750LL)*fps);

		mvid_val = (((1650LL*750LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_2 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_2 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_2 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_2 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_2 , 1650);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_2 register written with value: 1650\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_2 , 750);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_2 register written with value: 750\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_2 , 1280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_2 register written with value: 1280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_2 , 720);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_2 register written with value: 720\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_2 , 330);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_2 register written with value: 330\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_2 , 25);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_2 register written with value: 25\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_2 , 40);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_2 register written with value: 40\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_2 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_2 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_2 , 370);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_2 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_2 , 30);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_2 register written with value: 30\r\n");
#endif
		}
	}
	else if(resolution == 1){
		// resolution 1920x1080p

		peak_stream_bandwidth = bpp*((2200LL*1125LL)*fps);

		mvid_val = (((2200LL*1125LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_2 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_2 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_2 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_2 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_2 , 2200);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_2 register written with value: 2200\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_2 , 1125);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_2 register written with value: 1125\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_2 , 1920);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_2 register written with value: 1920\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_2 , 1080);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_2 register written with value: 1080\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_2 , 192);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_2 register written with value: 192\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_2 , 41);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_2 register written with value: 41\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_2 , 44);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_2 register written with value: 44\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_2 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_2 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_2 , 280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_2 register written with value: 280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_2 , 45);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_2 register written with value: 45\r\n");
#endif
		}
	}
	else
	{
		// resolution 3840x2160p

		peak_stream_bandwidth = bpp*((4400LL*2250LL)*fps);


		mvid_val = (((4400LL*2250LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_2 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_2 register written with value: %u\r\n" ,mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_2 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_2 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_2 , 4400);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_2 register written with value: 4400\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_2 , 2250);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_2 register written with value: 2250\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_2 , 3840);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_2 register written with value: 3840\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_2 , 2160);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_2 register written with value: 2160\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_2 , 384);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_2 register written with value: 384\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_2 , 82);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_2 register written with value: 82\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_2 , 88);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_2 register written with value: 88\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_2 , 10);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_2 register written with value: 10\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_2 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_2 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_2 , 560);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_2 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_2 , 90);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_2 register written with value: 30\r\n");
#endif
		}
	}

            val2 = 8.0 * Max_lane_count * Max_lane_rate * 27LL *1000000LL;
        	avg_valid_symbols_per_TU = (((peak_stream_bandwidth) / (val2)) * 64);
        	ts_int  = (int)(avg_valid_symbols_per_TU);
            Stream_ts_count = (ceil)(avg_valid_symbols_per_TU);
        	val1    = (avg_valid_symbols_per_TU)-(int)(avg_valid_symbols_per_TU);
            cnt     = 4;
            ts_frac = 0;
        while (cnt >0) {
                	val1    = val1*2;
                	ts_frac = ts_frac + ((int)(val1))*(1<<(cnt-1));
                	val1    = val1 -(int)(val1);
                    cnt     -=1 ;
                    if(cnt==0){
                    	ts_frac +=1;
                    	if(ts_frac==16){
                    		ts_frac=0;
                    		ts_int+=1;
                    	}
                    }
                };


	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_INT_2 , ts_int);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_INT_2 register written with value: %u\r\n", ts_int);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_FRAC_2 , ts_frac);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_FRAC_2 register written with value: %u\r\n", ts_frac);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_STREAM2_TS_COUNT , (int)Stream_ts_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_STREAM1_TS_COUNT_2 register written with value: %u\r\n", (int)Stream_ts_count);
#endif
	}

	return NO_ERROR;

}

/**@brief	This API  configures TX Stream 3 MSA parameters.
 * @param 	resolution 0 for 720p , 1 for 1080p and 2 for 4k.
 * @param	pixel_format to calculate bpp.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA_Stream_3 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int fps = 60;
	unsigned int mvid_val;
	unsigned int pll_refclk_lock;
	unsigned int pll_vidclk_lock;
	unsigned int misc0;
	unsigned int Max_lane_rate;
	unsigned int Max_lane_count;
	unsigned int ppc;
	unsigned int bpp;
	unsigned int cnt=4;

	double peak_stream_bandwidth;
	double PBN;
	double val1;
	double val2;
	double avg_valid_symbols_per_TU;
	unsigned int Stream_ts_count;
	unsigned int ts_int;
	unsigned int ts_frac;

	// MISC0 and MISC1 allocation
	DP_TX_Configure_MISC(3,bpc,pixel_format);

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW, &Max_lane_rate);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_rate read :  0x%02X\r\n" , Max_lane_rate);
#endif
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT, &Max_lane_count);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_count read :  0x%x\r\n" , Max_lane_count);
#endif
	}

	if((pixel_format == 0)||(pixel_format==1)){// RGB/YCbCr444
		bpp = 3*bpc;
	}else if(pixel_format == 2){// YCbCr422
		bpp = 2*bpc;
	}else if(pixel_format == 3){//RAW
		bpp = 1*bpc;
	}

	// resolution 1280x720p
	if (resolution == 0)
	{

		peak_stream_bandwidth = bpp*((1650LL*750LL)*fps);

		mvid_val = (((1650LL*750LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_3 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_3 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_3 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_3 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_3 , 1650);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_3 register written with value: 1650\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_3 , 750);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_3 register written with value: 750\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_3 , 1280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_3 register written with value: 1280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_3 , 720);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_3 register written with value: 720\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_3 , 330);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_3 register written with value: 330\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_3 , 25);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_3 register written with value: 25\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_3 , 40);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_3 register written with value: 40\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_3 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_3 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_3 , 370);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_3 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_3 , 30);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_3 register written with value: 30\r\n");
#endif
		}
	}
	else if(resolution == 1){
		// resolution 1920x1080p

		peak_stream_bandwidth = bpp*((2200LL*1125LL)*fps);

		mvid_val = (((2200LL*1125LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_3 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_3 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_3 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_3 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_3 , 2200);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_3 register written with value: 2200\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_3 , 1125);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_3 register written with value: 1125\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_3 , 1920);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_3 register written with value: 1920\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_3 , 1080);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_3 register written with value: 1080\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_3 , 192);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_3 register written with value: 192\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_3 , 41);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_3 register written with value: 41\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_3 , 44);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_3 register written with value: 44\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_3 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_3 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_3 , 280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_3 register written with value: 280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_3 , 45);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_3 register written with value: 45\r\n");
#endif
		}
	}
	else
	{
		// resolution 3840x2160p
		peak_stream_bandwidth = bpp*((4400LL*2250LL)*fps);

		mvid_val = (((4400LL*2250LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_3 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_3 register written with value: %u\r\n" ,mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_3 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_3 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_3 , 4400);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_3 register written with value: 4400\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_3 , 2250);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_3 register written with value: 2250\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_3 , 3840);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_3 register written with value: 3840\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_3 , 2160);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_3 register written with value: 2160\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_3 , 384);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_3 register written with value: 384\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_3 , 82);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_3 register written with value: 82\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_3 , 88);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_3 register written with value: 88\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_3 , 10);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_3 register written with value: 10\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_3 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_3 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_3 , 560);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_3 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_3 , 90);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_3 register written with value: 30\r\n");
#endif
		}
	}

	        val2 = 8.0 * Max_lane_count * Max_lane_rate * 27LL *1000000LL;
        	avg_valid_symbols_per_TU = (((peak_stream_bandwidth) / (val2)) * 64);
        	ts_int  = (int)(avg_valid_symbols_per_TU);
            Stream_ts_count = (avg_valid_symbols_per_TU +1);
        	val1    = (avg_valid_symbols_per_TU)-(int)(avg_valid_symbols_per_TU);
            cnt     = 4;
            ts_frac = 0;
        while (cnt >0) {
                	val1    = val1*2;
                	ts_frac = ts_frac + ((int)(val1))*(1<<(cnt-1));
                	val1    = val1 -(int)(val1);
                    cnt     -=1 ;
                    if(cnt==0){
                    	ts_frac +=1;
                    	if(ts_frac==16){
                    		ts_frac=0;
                    		ts_int+=1;
                    	}
                    }
                };

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_INT_3 , ts_int);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_INT_3 register written with value: %u\r\n", ts_int);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_FRAC_3 , ts_frac);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_FRAC_3 register written with value: %u\r\n", ts_frac);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_STREAM3_TS_COUNT , (int)Stream_ts_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_STREAM3_TS_COUNT register written with value: %u\r\n", (int)Stream_ts_count);
#endif
	}

	return NO_ERROR;
}

/**@brief	This API  configures TX Stream 4 MSA parameters.
 * @param 	resolution 0 for 720p , 1 for 1080p and 2 for 4k.
 * @param	pixel_format to calculate bpp.
 * @return 	Returns NO_ERROR on success
 */
unsigned char DP_TX_Configure_MSA_Stream_4 (unsigned int resolution , unsigned int bpc, unsigned int pixel_format){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int fps = 60;
	unsigned int mvid_val;
	unsigned int pll_refclk_lock;
	unsigned int pll_vidclk_lock;
	unsigned int misc0;
	unsigned int Max_lane_rate;
	unsigned int Max_lane_count;
	unsigned int ppc;
	unsigned int bpp;
	unsigned int cnt=4;

	double peak_stream_bandwidth;
	double PBN;
	double val1;
	double val2;
	double avg_valid_symbols_per_TU;
	unsigned int Stream_ts_count;
	unsigned int ts_int;
	unsigned int ts_frac;

	// MISC0 and MISC1 allocation
	DP_TX_Configure_MISC(4,bpc,pixel_format);

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_BW, &Max_lane_rate);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_rate read :  0x%02X\r\n" , Max_lane_rate);
#endif
	}

	ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_LANE_COUNT, &Max_lane_count);
	if (ret == 0) {
#if REG_READ_DEBUG
		printf("Max_lane_count read :  0x%x\r\n" , Max_lane_count);
#endif
	}

	if((pixel_format == 0)||(pixel_format==1)){// RGB/YCbCr444
		bpp = 3*bpc;
	}else if(pixel_format == 2){// YCbCr422
		bpp = 2*bpc;
	}else if(pixel_format == 3){//RAW
		bpp = 1*bpc;
	}

	// resolution 1280x720p
	if (resolution == 0)
	{

		peak_stream_bandwidth = bpp*((1650LL*750LL)*fps);

		mvid_val = (((1650LL*750LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_4 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_4 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_4 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_4 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_4 , 1650);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_4 register written with value: 1650\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_4 , 750);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_4 register written with value: 750\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_4 , 1280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_4 register written with value: 1280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_4 , 720);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_4 register written with value: 720\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_4 , 330);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_4 register written with value: 330\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_4 , 25);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_4 register written with value: 25\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_4 , 40);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_4 register written with value: 40\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_4 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_4 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_4 , 370);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_4 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_4 , 30);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_4 register written with value: 30\r\n");
#endif
		}
	}
	else if(resolution == 1){
		// resolution 1920x1080p

		peak_stream_bandwidth = bpp*((2200LL*1125LL)*fps);

		mvid_val = (((2200LL*1125LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_4 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_4 register written with value: %u\r\n" , mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_4 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_4 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_4 , 2200);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_4 register written with value: 2200\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_4 , 1125);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_4 register written with value: 1125\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_4 , 1920);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_4 register written with value: 1920\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_4 , 1080);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_4 register written with value: 1080\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_4 , 192);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_4 register written with value: 192\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_4 , 41);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_4 register written with value: 41\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_4 , 44);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_4 register written with value: 44\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_4 , 5);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_4 register written with value: 5\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_4 , 280);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_4 register written with value: 280\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_4 , 45);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_4 register written with value: 45\r\n");
#endif
		}
	}
	else
	{
		// resolution 3840x2160p

		peak_stream_bandwidth = bpp*((4400LL*2250LL)*fps);

		mvid_val = (((4400LL*2250LL)*fps)*32768LL)/(27*Max_lane_rate*1000000LL);
		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_MVID_4 , mvid_val);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_MVID_4 register written with value: %u\r\n" ,mvid_val);
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_NVID_4 , 32768);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_NVID_4 register written with value: 32768\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HTOTAL_4 , 4400);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HTOTAL_4 register written with value: 4400\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VTOTAL_4 , 2250);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VTOTAL_4 register written with value: 2250\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HWIDTH_4 , 3840);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HWIDTH_4 register written with value: 3840\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VHEIGHT_4 , 2160);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VHEIGHT_4 register written with value: 2160\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSTART_4 , 384);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSTART_4 register written with value: 384\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSTART_4 , 82);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSTART_4 register written with value: 82\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_WIDTH_4 , 88);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_WIDTH_4 register written with value: 88\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_WIDTH_4 , 10);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_WIDTH_4 register written with value: 10\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VSYNC_POLARITY_4 , 0);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VSYNC_POLARITY_4 register written with value: 0\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_HBLANK_4 , 560);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_HBLANK_4 register written with value: 370\r\n");
#endif
		}

		ret = DP_RegAccessWrite (DP_TX_REG_BASE_ADD , DP_TX_VBLANK_4 , 90);
		if (ret ==0) {
#if REG_WRITE_DEBUG
			printf("DP_TX_VBLANK_4 register written with value: 30\r\n");
#endif
		}
	}

            val2 = 8.0 * Max_lane_count * Max_lane_rate * 27LL *1000000LL;
        	avg_valid_symbols_per_TU = (((peak_stream_bandwidth) / (val2)) * 64);
        	ts_int  = (int)(avg_valid_symbols_per_TU);
            Stream_ts_count = (ceil)(avg_valid_symbols_per_TU);
        	val1    = (avg_valid_symbols_per_TU)-(int)(avg_valid_symbols_per_TU);
            cnt     = 4;
            ts_frac = 0;
        while (cnt >0) {
                	val1    = val1*2;
                	ts_frac = ts_frac + ((int)(val1))*(1<<(cnt-1));
                	val1    = val1 -(int)(val1);
                    cnt     -=1 ;
                    if(cnt==0){
                    	ts_frac +=1;
                    	if(ts_frac==16){
                    		ts_frac=0;
                    		ts_int+=1;
                    	}
                    }
                };


	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_INT_4 , ts_int);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_INT_4 register written with value: %u\r\n", ts_int);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_TS_FRAC_4 , ts_frac);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_TS_FRAC_4 register written with value: %u\r\n", ts_frac);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_STREAM4_TS_COUNT , (int)Stream_ts_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_STREAM4_TS_COUNT register written with value: %u\r\n", (int)Stream_ts_count);
#endif
	}

	return NO_ERROR;
}


unsigned char DP_TX_Link_Address(unsigned int port_number , unsigned int vc_payload_id , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *number_of_port ,  UInt128 *result){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int count;
	unsigned int GUID1;
	unsigned int GUID2;
	unsigned int GUID3;
	unsigned int GUID4;


	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_REPLY_INDENTIFIER , LINK_ADDRESS);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_REPLY_INDENTIFIER register written with value: %u\r\n", LINK_ADDRESS);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_1 , RAD1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_1 register written with value: %u\r\n", RAD1);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_2 , RAD2);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_2 register written with value: %u\r\n", RAD2);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_LINK_COUNT , link_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_LINK_COUNT register written with value: %u\r\n", link_count);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REQUEST_INITIATE , 1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_DOWN_REQUEST_INITIATE register written with value: %u\r\n", 1);
#endif
	}

	count = 0;
	while(count < 50) {
		ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REPLY_READY, &reg_val);
		if(ret == 0 && reg_val == 0x1) {
			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_LINK_ADDR_REPLY_DATA_N_PORTS, number_of_port);
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_LINK_ADDR_REPLY_DATA_N_PORTS read :  0x%x\r\n" , number_of_port);
#endif
			}

			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_LINK_ADDR_REPLY_DATA_GUID1, &(result->GUID1));
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_LINK_ADDR_REPLY_DATA_GUID1 read :  0x%x\r\n" , (result->GUID1));
#endif
			}

			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_LINK_ADDR_REPLY_DATA_GUID2, &(result->GUID2));
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_LINK_ADDR_REPLY_DATA_GUID2 read :  0x%x\r\n" , (result->GUID2));
#endif
			}
			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_LINK_ADDR_REPLY_DATA_GUID3, &(result->GUID3));
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_LINK_ADDR_REPLY_DATA_GUID3 read :  0x%x\r\n" , (result->GUID3));
#endif
			}
			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_LINK_ADDR_REPLY_DATA_GUID4, &(result->GUID4));
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_LINK_ADDR_REPLY_DATA_GUID4 read :  0x%x\r\n" , (result->GUID4));
#endif
			}

			result->GUID = ((unsigned long long)result->GUID1 << 96) |((unsigned long long)result->GUID2 << 64) |
				   	   	   ((unsigned long long)result->GUID3 << 32) |(result->GUID4);

			printf("Combined GUID 128-bit value: 0x%016llx\n", result->GUID);

			break;
		}
		delayMS(1); // wait for 1ms
		count++;
		if(count == 50) {
			printf("Could not get Down Reply Ready\r\n");
		}
	}

	return NO_ERROR;
}


unsigned char DP_TX_Allocate_Payload(unsigned int port_number , unsigned int vc_payload_id ,unsigned int bpc, unsigned int pixel_clock_frequency, unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *alloc_reply ){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int count;
	unsigned int pbn;
	DP_TX_PBN_Calculation(bpc ,  pixel_clock_frequency , &pbn);

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_ALLOC_REQ_ALLOCATE_PBN , pbn);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_ALLOC_REQ_ALLOCATE_PBN register written with value: %u\r\n", pbn);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_ALLOC_REQ_PORT_NUMBER , port_number);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_ALLOC_REQ_PORT_NUMBER register written with value: %u\r\n", port_number);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_ALLOC_REQ_VC_PAYLOAD_ID , vc_payload_id);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_ALLOC_REQ_VC_PAYLOAD_ID register written with value: %u\r\n", vc_payload_id);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_REPLY_INDENTIFIER , ALLOCATE_PAYLOAD);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_REPLY_INDENTIFIER register written with value: %u\r\n", ALLOCATE_PAYLOAD);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_1 , RAD1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_1 register written with value: %u\r\n", RAD1);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_2 , RAD2);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_2 register written with value: %u\r\n", RAD2);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_LINK_COUNT , link_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_LINK_COUNT register written with value: %u\r\n", link_count);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REQUEST_INITIATE , 1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_DOWN_REQUEST_INITIATE register written with value: %u\r\n", 1);
#endif
	}

	count = 0;
	while(count < 50) {
		ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REPLY_READY, &reg_val);
		if(ret == 0 && reg_val == 0x1) {
			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_ALLOC_REPLY, alloc_reply);
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_ENUM_PATH_REPLY read :  0x%x\r\n" , alloc_reply);
#endif
			}
			break;
		}
		delayMS(1); // wait for 1ms
		count++;
		if(count == 50) {
			printf("Could not get Down Reply Ready\r\n");
		}
	}

	return NO_ERROR;

}

unsigned char DP_TX_Enum_Path_Resources(unsigned int port_number , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *enum_path_reply ){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int count;

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_ENUM_PATH_REQ_PORT_NUMBER , port_number);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_ENUM_PATH_REQ_PORT_NUMBER register written with value: %u\r\n", port_number);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_REPLY_INDENTIFIER , ENUM_PATH_RESOURCE);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_REPLY_INDENTIFIER register written with value: %u\r\n", ENUM_PATH_RESOURCE);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_1 , RAD1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_1 register written with value: %u\r\n", RAD1);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_2 , RAD2);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_2 register written with value: %u\r\n", RAD2);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_LINK_COUNT , link_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_LINK_COUNT register written with value: %u\r\n", link_count);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REQUEST_INITIATE , 1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_DOWN_REQUEST_INITIATE register written with value: %u\r\n", 1);
#endif
	}

	count = 0;
	while(count < 50) {
		ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REPLY_READY, &reg_val);
		if(ret == 0 && reg_val == 0x1) {
			ret = DP_RegAccessRead(DP_TX_REG_BASE_ADD , DP_TX_ENUM_PATH_REPLY, enum_path_reply);
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("DP_TX_ENUM_PATH_REPLY read :  0x%x\r\n" , enum_path_reply);
#endif
			}
			break;
		}
		delayMS(1); // wait for 1ms
		count++;
		if(count == 50) {
			printf("Could not get Down Reply Ready\r\n");
		}
	}


	return NO_ERROR;
}

unsigned char DP_TX_Connection_Status_Notify(void){

	//TBD
	return NO_ERROR;
}

unsigned char DP_TX_PBN_Calculation(unsigned int bpc , unsigned int pixel_clock_frequency , unsigned int *pbn){

	unsigned int bpp;
	bpp = 3 * bpc;
	*pbn = ceil(pixel_clock_frequency * bpp * (64.0/54.0));

	return NO_ERROR;
}

unsigned char DP_TX_Clear_Payload_Table(unsigned int port_number , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *clear_payload_id_reply ){

	unsigned int ret;
	unsigned int reg_val;
	unsigned int count;

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_REPLY_INDENTIFIER , CLEAR_PAYLOAD_ID_TABLE);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_REPLY_INDENTIFIER register written with value: %u\r\n", CLEAR_PAYLOAD_ID_TABLE);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_1 , RAD1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_1 register written with value: %u\r\n", RAD1);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_RELATIVE_ADDRESS_2 , RAD2);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_RELATIVE_ADDRESS_2 register written with value: %u\r\n", RAD2);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_LINK_COUNT , link_count);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_LINK_COUNT register written with value: %u\r\n", link_count);
#endif
	}

	ret = DP_RegAccessWrite(DP_TX_REG_BASE_ADD , DP_TX_DOWN_REQUEST_INITIATE , 1);
	if (ret ==0) {
#if REG_WRITE_DEBUG
		printf("DP_TX_DOWN_REQUEST_INITIATE register written with value: %u\r\n", 1);
#endif
	}

	count = 0;
	while(count < 50) {
		ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_DOWN_REPLY_READY, &reg_val);
		if(ret == 0 && reg_val == 0x1) {
			ret = DP_RegAccessRead (DP_TX_REG_BASE_ADD , DP_TX_CLEAR_PAYLOAD_ID_REPY, clear_payload_id_reply);
			if (ret == 0) {
#if REG_READ_DEBUG
				printf("clear_payload_id_reply read :  0x%x\r\n" , clear_payload_id_reply);
#endif
			}
			break;
		}
		delayMS(1); // wait for 1ms
		count++;
		if(count == 50) {
			printf("Could not get Down Reply Ready\r\n");
		}
	}

	return NO_ERROR;
}