/* ================================================================== >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< ------------------------------------------------------------------ Copyright (c) 2019-2020 by Lattice Semiconductor Corporation ALL RIGHTS RESERVED ------------------------------------------------------------------ IMPORTANT: THIS FILE IS USED BY OR GENERATED BY the LATTICE PROPEL™ DEVELOPMENT SUITE, WHICH INCLUDES PROPEL BUILDER AND PROPEL SDK. Lattice grants permission to use this code pursuant to the terms of the Lattice Propel License Agreement. DISCLAIMER: LATTICE MAKES NO WARRANTIES ON THIS FILE OR ITS CONTENTS, WHETHER EXPRESSED, IMPLIED, STATUTORY, OR IN ANY PROVISION OF THE LATTICE PROPEL LICENSE AGREEMENT OR COMMUNICATION WITH LICENSEE, AND LATTICE SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 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LATTICE 'S SOLE LIABILITY, AND LICENSEE' S SOLE REMEDY, IS SET FORTH ABOVE. LATTICE DOES NOT WARRANT OR REPRESENT THAT THIS FILE, ITS CONTENTS OR USE THEREOF DOES NOT INFRINGE ON THIRD PARTIES' INTELLECTUAL PROPERTY RIGHTS, INCLUDING ANY PATENT. IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ #include "hal.h" #include #include "sys_platform.h" #include #include "utils.h" #define BASE_ADDRESS_DP_TX_REG 0x00000 #define BASE_ADDRESS_MPCS_REG 0x10000 #define BASE_ADDRESS_VTG_REG 0x20000 #define BASE_ADDRESS_DP_RX_REG 0x30000 #define DP_TX_REG_BASE_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_DP_TX_REG) #define DP_MPCS_REG_BASE_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_MPCS_REG) #define DP_VTG_REG_BASE_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_VTG_REG) #define DP_EXTERNAL_REG_BASE_ADD (PLL_PROG0_INST_BASE_ADDR) #define DP_RX_REG_BASE_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_DP_RX_REG) #define DP_VIDEO_SCALER_REG_BASE_ADD (IP_SCALER_INST_BASE_ADDR) #define NUMBER_OF_EDID_REGISTERS 64 #define TX_NUMBER_OF_EDID_REGISTERS 256 #define RX_EDID_BASE_ADD 0x100 #define RX_EDID_STARTING_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_DP_RX_REG + RX_EDID_BASE_ADD) #define TX_EDID_BASE_ADD 0xEC //0xF0 - old #define TX_EDID_STARTING_ADD (DP_RX_TX0_INST_BASE_ADDR + BASE_ADDRESS_DP_TX_REG + TX_EDID_BASE_ADD) #define REG16_DEF(adds, start, end) ((adds << 16) | (start << 8) | (end-start+1)) //#define TESTCODE 1 #define REG_WRITE_DEBUG 1 #define REG_READ_DEBUG 1 //Reply indentifier values #define CLEAR_PAYLOAD_ID_TABLE 0X14 #define LINK_ADDRESS 0X01 #define CONNECTION_STATUS_NOTIFY 0X02 #define ALLOCATE_PAYLOAD 0X10 #define ENUM_PATH_RESOURCE 0X11 /** * @brief enumeration for the register space (register map) */ typedef enum { //DP TX Register Space //BASE ADDRESS: BASE ADDRESS OF DP + 0x000000 DP_TX_REV = REG16_DEF(0X0, 0, 29), DP_TX_DEMO_SELECTION = REG16_DEF(0X0, 30, 31), DP_TX_REL_DATE = REG16_DEF(0X4, 0, 31), DP_TX_MVID = REG16_DEF(0X8, 0, 23), DP_TX_NVID = REG16_DEF(0XC, 0, 23), DP_TX_HTOTAL = REG16_DEF(0X10, 0, 15), DP_TX_VTOTAL = REG16_DEF(0X10, 16, 31), DP_TX_HWIDTH = REG16_DEF(0X14, 0, 15), DP_TX_VHEIGHT = REG16_DEF(0X14, 16, 31), DP_TX_HSTART = REG16_DEF(0X18, 0, 15), DP_TX_VSTART = REG16_DEF(0X18, 16, 31), DP_TX_HSYNC_WIDTH = REG16_DEF(0X1C, 0, 14), DP_TX_VSYNC_WIDTH = REG16_DEF(0X1C, 15, 29), DP_TX_HSYNC_POLARITY = REG16_DEF(0X1C, 30, 30), DP_TX_VSYNC_POLARITY = REG16_DEF(0X1C, 31, 31), DP_TX_MISC0 = REG16_DEF(0X20, 0, 7), DP_TX_MISC1 = REG16_DEF(0X20, 8, 15), DP_TX_ENHANCED_MODE_EN = REG16_DEF(0X20, 16, 16), DP_TX_LANE_VALID = REG16_DEF(0X20, 17, 17), DP_TX_SST_OR_MST_MODE = REG16_DEF(0X20, 18, 19), DP_TX_SET_TO_TPS2 = REG16_DEF(0X20, 20, 20), DP_TX_SET_TO_TPS3 = REG16_DEF(0X20, 21, 21), DP_TX_SET_TO_TPS4 = REG16_DEF(0X20, 22, 22), DP_TX_IP_ACTIVE = REG16_DEF(0X20, 23, 23), DP_TX_EDID_BYPASS = REG16_DEF(0X20, 24, 24), DP_TX_IP_RETRAIN = REG16_DEF(0x20, 25, 25), DP_TX_HBLANK = REG16_DEF(0X24, 0, 15), DP_TX_VBLANK = REG16_DEF(0X24, 16, 31), DP_TX_LANE_BW = REG16_DEF(0X28, 0, 7), DP_TX_LANE_COUNT = REG16_DEF(0X28, 8, 12), DP_TX_TU_SIZE_IN_SYMBOL_COUNT = REG16_DEF(0X28, 13, 20), DP_TX_AVG_VALID_SYMBOLS_PER_TU = REG16_DEF(0X28, 21, 28), DP_TX_SPEAKER_MAPPING = REG16_DEF(0X30, 0, 7), DP_TX_AUDIO_CHANNEL_COUNT = REG16_DEF(0X30, 8, 11), DP_TX_AUDIO_SAMPLE_SIZE = REG16_DEF(0X30, 12, 13), DP_TX_AUDIO_SAMPLING_FREQ = REG16_DEF(0X30, 14, 16), DP_TX_AUDIO_ENABLE = REG16_DEF(0X30, 24, 24), DP_TX_MAUD = REG16_DEF(0X34, 0, 23), DP_TX_NAUD = REG16_DEF(0X38, 0, 23), DP_TX_HPD_FROM_SINK = REG16_DEF(0XB4, 8, 8), DP_TX_AUX_INF_READY = REG16_DEF(0XB4, 9, 9), DP_TX_TRAIN_BIT = REG16_DEF(0XB4, 10, 10), DP_TX_GTX_RST_DONE = REG16_DEF(0XB4, 11, 11), DP_TX_BPC = REG16_DEF(0XB4, 12, 16), DP_TX_TS_TRANSMIT = REG16_DEF(0XB4, 17, 19), DP_TX_TX_STATE = REG16_DEF(0XB4, 20, 22), DP_TX_DPCD_REVISION = REG16_DEF(0XC8, 0, 7), DP_TX_CHANNEL_COADING = REG16_DEF(0XC8, 8, 8), DP_TX_MAX_LAN_RATE = REG16_DEF(0xCC, 0, 7), DP_TX_MAX_LAN_COUNT = REG16_DEF(0xCC, 8, 12), DP_TX_TRAINING_RD_INTERVAL = REG16_DEF(0xCC, 13, 20), DP_TX_EDP_SUPPORT = REG16_DEF(0xCC, 21, 21), DP_TX_ENHANCE_MODE = REG16_DEF(0xCC, 22, 22), DP_TX_TPS3_SUPPORTED = REG16_DEF(0XD0, 0, 0), DP_TX_TPS4_SUPPORTED = REG16_DEF(0XD0, 1, 1), DP_TX_NO_AUX_TRANS_LINK_TRAIN = REG16_DEF(0XD0, 2, 2), DP_TX_RX_SUPPORT_MST = REG16_DEF(0XD0, 3, 3), DP_TX_I2C_SPEED_CAP = REG16_DEF(0XD0, 4, 11), DP_TX_LOCAL_EDID = REG16_DEF(0XD0, 12, 12), DP_TX_EXTENDED_RX_CAPABILITY = REG16_DEF(0XD0, 13, 13), DP_TX_EDID_H_VISIBLE = REG16_DEF(0XD4, 0, 15), DP_TX_EDID_H_BLANK = REG16_DEF(0XD4, 16, 31), DP_TX_EDID_V_VISIBLE = REG16_DEF(0XDC, 0, 15), DP_TX_EDID_V_BLANK = REG16_DEF(0XDC, 16, 31), DP_TX_TS_INT = REG16_DEF(0X3C, 0, 5), DP_TX_TS_FRAC = REG16_DEF(0X3C, 6, 9), DP_TX_STREAM1_TS_COUNT = REG16_DEF(0X3C, 10, 15), DP_TX_VC_PAYLOAD_ID_EN_1 = REG16_DEF(0X3C, 16, 16), DP_TX_VC_PAYLOAD_ID_EN_2 = REG16_DEF(0X3C, 17, 17), DP_TX_VC_PAYLOAD_ID_EN_3 = REG16_DEF(0X3C, 18, 18), DP_TX_VC_PAYLOAD_ID_EN_4 = REG16_DEF(0X3C, 19, 19), DP_TX_MVID_2 = REG16_DEF(0X40, 0, 23), DP_TX_NVID_2 = REG16_DEF(0X44, 0, 23), DP_TX_HTOTAL_2 = REG16_DEF(0X48, 0, 15), DP_TX_VTOTAL_2 = REG16_DEF(0X48, 16, 31), DP_TX_HWIDTH_2 = REG16_DEF(0X4C, 0, 15), DP_TX_VHEIGHT_2 = REG16_DEF(0X4C, 16, 31), DP_TX_HSTART_2 = REG16_DEF(0X50, 0, 15), DP_TX_VSTART_2 = REG16_DEF(0X50, 16, 31), DP_TX_HSYNC_WIDTH_2 = REG16_DEF(0X54, 0, 14), DP_TX_VSYNC_WIDTH_2 = REG16_DEF(0X54, 15, 29), DP_TX_HSYNC_POLARITY_2 = REG16_DEF(0X54, 30, 30), DP_TX_VSYNC_POLARITY_2 = REG16_DEF(0X54, 31, 31), DP_TX_MISC0_2 = REG16_DEF(0X58, 0, 7), DP_TX_MISC1_2 = REG16_DEF(0X58, 8, 15), DP_TX_TS_INT_2 = REG16_DEF(0X58, 16, 21), DP_TX_TS_FRAC_2 = REG16_DEF(0X58, 22, 25), DP_TX_STREAM2_TS_COUNT = REG16_DEF(0X58, 26, 31), DP_TX_HBLANK_2 = REG16_DEF(0X5C, 0, 15), DP_TX_VBLANK_2 = REG16_DEF(0X5C, 16, 31), DP_TX_MVID_3 = REG16_DEF(0X60, 0, 23), DP_TX_NVID_3 = REG16_DEF(0X64, 0, 23), DP_TX_HTOTAL_3 = REG16_DEF(0X68, 0, 15), DP_TX_VTOTAL_3 = REG16_DEF(0X68, 16, 31), DP_TX_HWIDTH_3 = REG16_DEF(0X6C, 0, 15), DP_TX_VHEIGHT_3 = REG16_DEF(0X6C, 16, 31), DP_TX_HSTART_3 = REG16_DEF(0X70, 0, 15), DP_TX_VSTART_3 = REG16_DEF(0X70, 16, 31), DP_TX_HSYNC_WIDTH_3 = REG16_DEF(0X74, 0, 14), DP_TX_VSYNC_WIDTH_3 = REG16_DEF(0X74, 15, 29), DP_TX_HSYNC_POLARITY_3 = REG16_DEF(0X74, 30, 30), DP_TX_VSYNC_POLARITY_3 = REG16_DEF(0X74, 31, 31), DP_TX_MISC0_3 = REG16_DEF(0X78, 0, 7), DP_TX_MISC1_3 = REG16_DEF(0X78, 8, 15), DP_TX_TS_INT_3 = REG16_DEF(0X78, 16, 21), DP_TX_TS_FRAC_3 = REG16_DEF(0X78, 22, 25), DP_TX_STREAM3_TS_COUNT = REG16_DEF(0X78, 26, 31), DP_TX_HBLANK_3 = REG16_DEF(0X7C, 0, 15), DP_TX_VBLANK_3 = REG16_DEF(0X7C, 16, 31), DP_TX_MVID_4 = REG16_DEF(0X80, 0, 23), DP_TX_NVID_4 = REG16_DEF(0X84, 0, 23), DP_TX_HTOTAL_4 = REG16_DEF(0X88, 0, 15), DP_TX_VTOTAL_4 = REG16_DEF(0X88, 16, 31), DP_TX_HWIDTH_4 = REG16_DEF(0X8C, 0, 15), DP_TX_VHEIGHT_4 = REG16_DEF(0X8C, 16, 31), DP_TX_HSTART_4 = REG16_DEF(0X90, 0, 15), DP_TX_VSTART_4 = REG16_DEF(0X90, 16, 31), DP_TX_HSYNC_WIDTH_4 = REG16_DEF(0X94, 0, 14), DP_TX_VSYNC_WIDTH_4 = REG16_DEF(0X94, 15, 29), DP_TX_HSYNC_POLARITY_4 = REG16_DEF(0X94, 30, 30), DP_TX_VSYNC_POLARITY_4 = REG16_DEF(0X94, 31, 31), DP_TX_MISC0_4 = REG16_DEF(0X98, 0, 7), DP_TX_MISC1_4 = REG16_DEF(0X98, 8, 15), DP_TX_TS_INT_4 = REG16_DEF(0X98, 16, 21), DP_TX_TS_FRAC_4 = REG16_DEF(0X98, 22, 25), DP_TX_STREAM4_TS_COUNT = REG16_DEF(0X98, 26, 31), DP_TX_HBLANK_4 = REG16_DEF(0X9C, 0, 15), DP_TX_VBLANK_4 = REG16_DEF(0X9C, 16, 31), DP_TX_VC_PAYLOAD_ID_1 = REG16_DEF(0XA0, 0, 5), DP_TX_VC_PAYLOAD_ID_2 = REG16_DEF(0XA0, 6, 11), DP_TX_VC_PAYLOAD_ID_3 = REG16_DEF(0XA0, 12, 17), DP_TX_VC_PAYLOAD_ID_4 = REG16_DEF(0XA0, 18, 23), //MPCS Register Space Description //BASE ADDRESS: BASE ADDRESS OF DP + 0x010000 DP_TX_REV_MPCS = REG16_DEF(0x00, 0, 29), DP_TX_DEMO_SELECTION_MPCS = REG16_DEF(0x00, 30, 31), DP_TX_REL_DATE_MPCS = REG16_DEF(0x04, 0, 31), DP_TX_LANE_BW_MPCS = REG16_DEF(0x08, 0, 7), DP_TX_LANE_COUNT_MPCS = REG16_DEF(0x08, 8, 12), DP_TX_MPCS_CONFIG_SWITCH_MPCS = REG16_DEF(0x34, 0, 0), //VTG Register Space //BASE ADDRESS :BASE ADDRESS OF DP + 0x020000 DP_TX_HWIDTH_VTG = REG16_DEF(0X00, 0, 15), DP_TX_HBLANK_VTG = REG16_DEF(0X04, 0, 15), DP_TX_HFRONT_VTG = REG16_DEF(0X08, 0, 15), DP_TX_HSYNC_WIDTH_VTG = REG16_DEF(0X0C, 0, 14), DP_TX_VHEIGHT_VTG = REG16_DEF(0X10, 0, 15), DP_TX_VBLANK_VTG = REG16_DEF(0X14, 0, 15), DP_TX_VFRONT_VTG = REG16_DEF(0X18, 0, 15), DP_TX_VSYNC_WIDTH_VTG = REG16_DEF(0X1C, 0, 14), DP_TX_INTER_VTOTAL_EVEN_VTG = REG16_DEF(0X80, 0, 0), DP_TX_INTERLACE_PROG_VTG = REG16_DEF(0X80, 1, 1), DP_TX_INPUT_RESOLUTION_LOCKED_OR_NOT_VTG = REG16_DEF(0X80, 2, 2), DP_TX_FRAME_ERROR_STATUS_VTG = REG16_DEF(0X80, 3, 3), DP_TX_RESOLUTION_VTG = REG16_DEF(0X80, 5, 6), DP_TX_RESOLUTION_SELECTION_VTG = REG16_DEF(0X80, 7, 7), DP_TX_CLEAR_FRAME_ERROR_STATUS_VTG = REG16_DEF(0X80, 31, 31), DP_TX_PPC_VTG = REG16_DEF(0XA8, 0, 2), DP_TX_PIXEL_COUNT_VTG = REG16_DEF(0XAC, 0, 31), DP_TX_LINE_COUNT_VTG = REG16_DEF(0XB0, 0, 31), DP_TX_HWIDTH_VTG_2 = REG16_DEF(0X20, 0, 15), DP_TX_HBLANK_VTG_2 = REG16_DEF(0X24, 0, 15), DP_TX_HFRONT_VTG_2 = REG16_DEF(0X28, 0, 15), DP_TX_HSYNC_WIDTH_VTG_2 = REG16_DEF(0X2C, 0, 14), DP_TX_VHEIGHT_VTG_2 = REG16_DEF(0X30, 0, 15), DP_TX_VBLANK_VTG_2 = REG16_DEF(0X34, 0, 15), DP_TX_VFRONT_VTG_2 = REG16_DEF(0X38, 0, 15), DP_TX_VSYNC_WIDTH_VTG_2 = REG16_DEF(0X3C, 0, 14), DP_TX_HWIDTH_VTG_3 = REG16_DEF(0X40, 0, 15), DP_TX_HBLANK_VTG_3 = REG16_DEF(0X44, 0, 15), DP_TX_HFRONT_VTG_3 = REG16_DEF(0X48, 0, 15), DP_TX_HSYNC_WIDTH_VTG_3 = REG16_DEF(0X4C, 0, 14), DP_TX_VHEIGHT_VTG_3 = REG16_DEF(0X50, 0, 15), DP_TX_VBLANK_VTG_3 = REG16_DEF(0X54, 0, 15), DP_TX_VFRONT_VTG_3 = REG16_DEF(0X58, 0, 15), DP_TX_VSYNC_WIDTH_VTG_3 = REG16_DEF(0X5C, 0, 14), DP_TX_HWIDTH_VTG_4 = REG16_DEF(0X60, 0, 15), DP_TX_HBLANK_VTG_4 = REG16_DEF(0X64, 0, 15), DP_TX_HFRONT_VTG_4 = REG16_DEF(0X68, 0, 15), DP_TX_HSYNC_WIDTH_VTG_4 = REG16_DEF(0X6C, 0, 14), DP_TX_VHEIGHT_VTG_4 = REG16_DEF(0X70, 0, 15), DP_TX_VBLANK_VTG_4 = REG16_DEF(0X74, 0, 15), DP_TX_VFRONT_VTG_4 = REG16_DEF(0X78, 0, 15), DP_TX_VSYNC_WIDTH_VTG_4 = REG16_DEF(0X7C, 0, 14), //MST APIs related DP_TX_HPD_INTERRUPT = REG16_DEF(0XA0, 0, 0), DP_TX_DOWN_REPLY_READY = REG16_DEF(0XA0, 1, 1), DP_TX_RELATIVE_ADDRESS_1 = REG16_DEF(0XA4, 0, 31), DP_TX_RELATIVE_ADDRESS_2 = REG16_DEF(0XA8, 0, 31), DP_TX_DOWN_REQUEST_INITIATE = REG16_DEF(0XAC, 0, 0), DP_TX_LINK_COUNT = REG16_DEF(0XAC, 1, 4), DP_TX_REPLY_INDENTIFIER = REG16_DEF(0XAC, 5, 11), DP_TX_LINK_ADDR_REPLY_DATA_GUID1 = REG16_DEF(0XB0, 0, 31), DP_TX_LINK_ADDR_REPLY_DATA_GUID2 = REG16_DEF(0XB4, 0, 31), DP_TX_LINK_ADDR_REPLY_DATA_GUID3 = REG16_DEF(0XB8, 0, 31), DP_TX_LINK_ADDR_REPLY_DATA_GUID4 = REG16_DEF(0XBC, 0, 31), DP_TX_LINK_ADDR_REPLY_DATA_N_PORTS = REG16_DEF(0XC0, 0, 3), //C4 RESERVED DP_TX_ENUM_PATH_REQ_PORT_NUMBER = REG16_DEF(0XC8, 0, 3), DP_TX_ENUM_PATH_REPLY_PORT_NUMBER = REG16_DEF(0XCC, 0, 3), DP_TX_ENUM_PATH_REPLY_VC_PAYLOAD_ID = REG16_DEF(0XCC, 4, 4), DP_TX_ENUM_PATH_REPLY_FULL_PAYLOAD_BW = REG16_DEF(0XCC, 5, 15), DP_TX_ENUM_PATH_REPLY_AVAI_PAYLOAD_BW = REG16_DEF(0XCC, 16, 26), DP_TX_ENUM_PATH_REPLY = REG16_DEF(0XCC, 27, 30), DP_TX_ALLOC_REQ_PORT_NUMBER = REG16_DEF(0XD0, 0, 3), DP_TX_ALLOC_REQ_ALLOCATE_PBN = REG16_DEF(0XD0, 4, 19), DP_TX_ALLOC_REQ_VC_PAYLOAD_ID = REG16_DEF(0XD0, 20, 27), DP_TX_ALLOC_REPLY = REG16_DEF(0XD4, 0, 3), DP_TX_ALLOC_REPLY_ALLOC_PBN = REG16_DEF(0XD4, 4, 19), DP_TX_ALLOC_REPLY_VC_PAYLOAD_ID = REG16_DEF(0XD4, 20, 27), DP_TX_CLEAR_PAYLOAD_ID_REQ_PORT_NUMBER = REG16_DEF(0XD8, 0, 3), DP_TX_CLEAR_PAYLOAD_ID_REPY = REG16_DEF(0XD8, 0, 3), //EXTERNAL REGISTER SPACE DESCRIPTION //BASE_ADDRESS : BASE_ADDRESS from propel DP_TX_PLL_REF_CLK_LOCK_EX_REG = REG16_DEF(0X4, 0, 0), DP_TX_PLL_VID_CLK_LOCK_EX_REG = REG16_DEF(0X4, 1, 1), DP_TX_H_VISIBLE_EX_REG = REG16_DEF(0X8, 0, 15), DP_TX_H_BLANK_EX_REG = REG16_DEF(0X8, 16, 31), DP_TX_V_VISIBLE_EX_REG = REG16_DEF(0XC, 0, 15), DP_TX_V_BLANK_EX_REG = REG16_DEF(0XC, 16, 31), DP_TX_CLK_SELECTION_EX_REG = REG16_DEF(0X10, 0, 1), DP_TX_LINK_BW_EX_REG = REG16_DEF(0X10, 2, 9), DP_TX_RST_I2C_EX_REG = REG16_DEF(0X10, 10, 10), DP_TX_SOFT_RESET_EX_REG = REG16_DEF(0X14, 0, 0), DP_TX_PATTERN_EX_REG = REG16_DEF(0X14, 1, 2), DP_VS_INPUT_RESOLUTION_EX_REG = REG16_DEF(0X18, 0, 1), DP_VS_OUTPUT_RESOLUTION_EX_REG = REG16_DEF(0X1c, 0, 1), DP_VS_PATTERN_TYPE_EX_REG = REG16_DEF(0X20, 0, 1), DP_VS_PIXEL_CLK_O_EX_REG = REG16_DEF(0X24, 0, 1), DP_VS_PIXEL_CLK_1_EX_REG = REG16_DEF(0X24, 4, 5), //RX Enum //BASE ADDRESS :BASE ADDRESS OF DP + 0x030000 // MSA Data DP_RX_VERSION_REG = REG16_DEF(0X00, 0, 2), DP_RX_VERSION_NUMBER = REG16_DEF(0X00, 0, 31), DP_RX_VERSION_DATE = REG16_DEF(0X04, 0, 31), DP_RX_MVID_S0 = REG16_DEF(0X08, 0, 23), DP_RX_NVID_S0 = REG16_DEF(0X0C, 0, 23), DP_RX_HTOTAL_S0 = REG16_DEF(0X10, 0, 15), DP_RX_VTOTAL_S0 = REG16_DEF(0X10, 16, 31), DP_RX_HWIDTH_S0 = REG16_DEF(0X14, 0, 15), DP_RX_VHEIGHT_S0 = REG16_DEF(0X14, 16, 31), DP_RX_HSTART_S0 = REG16_DEF(0X18, 0, 15), DP_RX_VSTART_S0 = REG16_DEF(0X18, 16, 31), DP_RX_HSYNC_WIDTH_S0 = REG16_DEF(0X1C, 0, 14), DP_RX_VSYNC_WIDTH_S0 = REG16_DEF(0X1C, 16, 30), DP_RX_MISC0_S0 = REG16_DEF(0X20, 0, 7), DP_RX_MISC0_S0_BPC = REG16_DEF(0X20, 5, 7), DP_RX_PIX_FORMAT = REG16_DEF(0X20, 1, 2), DP_RX_MISC1_S0 = REG16_DEF(0X20, 8, 15), DP_RX_HSYNC_POLARITY_S0 = REG16_DEF(0X20, 16, 16), DP_RX_VSYNC_POLARITY_S0 = REG16_DEF(0X20, 17, 17), DP_RX_MSA_VALID_IN_S0 = REG16_DEF(0X20, 18, 18), DP_RX_MSA_FORMAT_ERROR_S0 = REG16_DEF(0X20, 19, 19), DP_RX_VB_ID_FORMAT_ERROR_S0 = REG16_DEF(0X20, 20, 20), DP_RX_PIXEL_COUNT_MISMATCH_FLAG_S0 = REG16_DEF(0X20, 21, 21), DP_RX_MVID_S1 = REG16_DEF(0X24, 0, 23), DP_RX_NVID_S1 = REG16_DEF(0X28, 0, 23), DP_RX_HTOTAL_S1 = REG16_DEF(0X2C, 0, 15), DP_RX_VTOTAL_S1 = REG16_DEF(0X2C, 16, 31), DP_RX_HWIDTH_S1 = REG16_DEF(0X30, 0, 15), DP_RX_VHEIGHT_S1 = REG16_DEF(0X30, 16, 31), DP_RX_HSTART_S1 = REG16_DEF(0X34, 0, 15), DP_RX_VSTART_S1 = REG16_DEF(0X34, 16, 31), DP_RX_HSYNC_WIDTH_S1 = REG16_DEF(0X38, 0, 14), DP_RX_VSYNC_WIDTH_S1 = REG16_DEF(0X38, 16, 30), DP_RX_MISC0_S1 = REG16_DEF(0X3C, 0, 7), DP_RX_MISC0_S1_BPC = REG16_DEF(0X3C, 5, 7), DP_RX_PIX_FORMAT_S1 = REG16_DEF(0X38, 1, 2), DP_RX_MISC1_S1 = REG16_DEF(0X38, 8, 15), DP_RX_HSYNC_POLARITY_S1 = REG16_DEF(0X3C, 16, 16), DP_RX_VSYNC_POLARITY_S1 = REG16_DEF(0X3C, 17, 17), DP_RX_MSA_VALID_IN_S1 = REG16_DEF(0X3C, 18, 18), DP_RX_MSA_FORMAT_ERROR_S1 = REG16_DEF(0X3C, 19, 19), DP_RX_VB_ID_FORMAT_ERROR_S1 = REG16_DEF(0X3C, 20, 20), DP_RX_MVID_S2 = REG16_DEF(0X40, 0, 23), DP_RX_NVID_S2 = REG16_DEF(0X44, 0, 23), DP_RX_HTOTAL_S2 = REG16_DEF(0X48, 0, 15), DP_RX_VTOTAL_S2 = REG16_DEF(0X48, 16, 31), DP_RX_HWIDTH_S2 = REG16_DEF(0X4C, 0, 15), DP_RX_VHEIGHT_S2 = REG16_DEF(0X4C, 16, 31), DP_RX_HSTART_S2 = REG16_DEF(0X50, 0, 15), DP_RX_VSTART_S2 = REG16_DEF(0X50, 16, 31), DP_RX_HSYNC_WIDTH_S2 = REG16_DEF(0X54, 0, 14), DP_RX_VSYNC_WIDTH_S2 = REG16_DEF(0X54, 16, 30), DP_RX_MISC0_S2 = REG16_DEF(0X58, 0, 7), DP_RX_MISC0_S2_BPC = REG16_DEF(0X58, 5, 7), DP_RX_PIX_FORMAT_S2 = REG16_DEF(0X58, 1, 2), DP_RX_MISC1_S2 = REG16_DEF(0X58, 8, 15), DP_RX_HSYNC_POLARITY_S2 = REG16_DEF(0X58, 16, 16), DP_RX_VSYNC_POLARITY_S2 = REG16_DEF(0X58, 17, 17), DP_RX_MSA_VALID_IN_S2 = REG16_DEF(0X58, 18, 18), DP_RX_MSA_FORMAT_ERROR_S2 = REG16_DEF(0X58, 19, 19), DP_RX_VB_ID_FORMAT_ERROR_S2 = REG16_DEF(0X58, 20, 20), DP_RX_MVID_S3 = REG16_DEF(0X5C, 0, 23), DP_RX_NVID_S3 = REG16_DEF(0X60, 0, 23), DP_RX_HTOTAL_S3 = REG16_DEF(0X64, 0, 15), DP_RX_VTOTAL_S3 = REG16_DEF(0X64, 16, 31), DP_RX_HWIDTH_S3 = REG16_DEF(0X68, 0, 15), DP_RX_VHEIGHT_S3 = REG16_DEF(0X68, 16, 31), DP_RX_HSTART_S3 = REG16_DEF(0X6C, 0, 15), DP_RX_VSTART_S3 = REG16_DEF(0X6C, 16, 31), DP_RX_HSYNC_WIDTH_S3 = REG16_DEF(0X70, 0, 14), DP_RX_VSYNC_WIDTH_S3 = REG16_DEF(0X70, 16, 30), DP_RX_MISC0_S3 = REG16_DEF(0X74, 0, 7), DP_RX_MISC0_S3_BPC = REG16_DEF(0X74, 5, 7), DP_RX_PIX_FORMAT_S3 = REG16_DEF(0X74, 1, 2), DP_RX_MISC1_S3 = REG16_DEF(0X74, 8, 15), DP_RX_HSYNC_POLARITY_S3 = REG16_DEF(0X74, 16, 16), DP_RX_VSYNC_POLARITY_S3 = REG16_DEF(0X74, 17, 17), DP_RX_MSA_VALID_IN_S3 = REG16_DEF(0X74, 18, 18), DP_RX_MSA_FORMAT_ERROR_S3 = REG16_DEF(0X74, 19, 19), DP_RX_VB_ID_FORMAT_ERROR_S3 = REG16_DEF(0X74, 20, 20), // Configuration by DPTX DP_RX_PHY_LANE_RATE = REG16_DEF(0X78, 0, 7), DP_RX_NO_OF_PHY_LANES = REG16_DEF(0X78, 8, 10), DP_RX_MPCS_READY = REG16_DEF(0X78, 11, 11), DP_RX_LINK_ERROR = REG16_DEF(0X78, 12, 12), DP_RX_TRAINING_DONE = REG16_DEF(0X78, 13, 13), DP_RX_RX_STATE_OUT = REG16_DEF(0X78, 14, 17), DP_RX_ENHANCED_MODE_EN = REG16_DEF(0X78, 18, 18), DP_RX_STREAM_COUNT_INT = REG16_DEF(0X78, 19, 19), DP_RX_RESOLUTION_LOCKED = REG16_DEF(0X78, 20, 20), DP_RX_RESOLUTION_LOCKED_S1 = REG16_DEF(0X78, 21, 21), DP_RX_RESOLUTION_LOCKED_S2 = REG16_DEF(0X78, 22, 22), DP_RX_RESOLUTION_LOCKED_S3 = REG16_DEF(0X78, 23, 23), DP_RX_EDID_CHECK_CAL_DONE = REG16_DEF(0X78, 24, 24), DP_RX_INTERLACE_SUPPORT_S0 = REG16_DEF(0X78, 25, 25), DP_RX_INTERLACE_SUPPORT_S1 = REG16_DEF(0X78, 26, 26), DP_RX_INTERLACE_SUPPORT_S2 = REG16_DEF(0X78, 27, 27), DP_RX_INTERLACE_SUPPORT_S3 = REG16_DEF(0X78, 28, 28), DP_RX_MAUD = REG16_DEF(0X7C, 0, 23), DP_RX_NAUD = REG16_DEF(0X80, 0, 23), DP_RX_AUDIO_CHANNEL_COUNT = REG16_DEF(0X84, 0, 2), DP_RX_AUDIO_FORMAT_TYPE = REG16_DEF(0X84, 3, 6), DP_RX_AUDIO_SAMPLE_SIZE = REG16_DEF(0X84, 7, 8), DP_RX_AUDIO_SAMPLE_FREQUENCY = REG16_DEF(0X84, 9, 11), DP_RX_AUDIO_STREAM_TYPE = REG16_DEF(0X84, 12, 16), DP_RX_AUDIO_SPEAKER_MAPPING = REG16_DEF(0X84, 17, 24), // Capability shown to DPTX DP_RX_VIDEO_RESOLUTION_IN = REG16_DEF(0X8C, 0, 4), DP_RX_HOST_LANE_COUNT_CAP = REG16_DEF(0X8C, 5, 7), DP_RX_HOST_RX_IP_ACTIVE = REG16_DEF(0X8C, 8, 8), DP_RX_HOST_LANE_RATE_CAP = REG16_DEF(0X8C, 9, 16), DP_RX_HOST_AUD_CAP = REG16_DEF(0X8C, 17, 17), DP_RX_HOST_ENHANCE_FRAME_CAP = REG16_DEF(0X8C, 18, 18), DP_RX_HOST_MST_SST_CAP = REG16_DEF(0X8C, 19, 19), DP_RX_EDP_ENABLE_CONFIG = REG16_DEF(0X8C, 20, 20), DP_RX_EDID_UPDATE = REG16_DEF(0X8C, 21, 21), DP_RX_FPS_VAL = REG16_DEF(0XB8, 5, 12), DP_RX_SCAN_TYPE = REG16_DEF(0XB8, 0, 0), //MST related DP_RX_RAD1 = REG16_DEF(0XA0, 0, 31), DP_RX_RAD2 = REG16_DEF(0XA4, 0, 31), DP_RX_GUID1 = REG16_DEF(0XA8, 0, 31), DP_RX_GUID2 = REG16_DEF(0XAC, 0, 31), DP_RX_GUID3 = REG16_DEF(0XB0, 0, 31), DP_RX_GUID4 = REG16_DEF(0XB4, 0, 31), DP_RX_PBN = REG16_DEF(0XB8, 0, 15), //VIDEO SCALER REGISTER SPACE DESCRIPTION DP_VS_FRMWIDTH = REG16_DEF(0X00, 0, 31), DP_VS_FRMHEIGHT = REG16_DEF(0X04, 0, 31), DP_VS_OUTWIDTH = REG16_DEF(0X08, 0, 31), DP_VS_OUTHEIGHT = REG16_DEF(0X0C, 0, 31), DP_VS_VSFACTOR = REG16_DEF(0X10, 0, 31), DP_VS_HSFACTOR = REG16_DEF(0X14, 0, 31), DP_VS_HBLANKOUT = REG16_DEF(0X18, 0, 31), DP_VS_VBLANKOUT = REG16_DEF(0X1C, 0, 31), DP_VS_UPDATE = REG16_DEF(0X20, 0, 31), }FPGARegsDefs; /** * @brief handle for AudioConfig * @brief 1.speaker_mapping - speaker mapping audio configuration parameter * @brief 2.channel_count - channel count audio configuration parameter * @brief 3.sampling_frequency - sampling frequency audio configuration parameter * @brief 4.sample_bit_size - sample bit size audio configuration parameter * @brief 5.maud - maud audio configuration parameter * @brief 6.naud - naud audio configuration parameter */ typedef struct { unsigned int speaker_mapping; unsigned int channel_count; unsigned int sampling_frequency; unsigned int sample_bit_size; unsigned int maud; unsigned int naud; } AudioConfig; /** * @brief handle for EDPConfig * @brief 1.enhanced_mode_en - enhanced mode enable oo Disable EDP configuration parameter * @brief 2.lane_rate - lane rate EDP configuration parameter * @brief 3.lane_count - lane count EDP configuration parameter * @brief 4.voltage_swing - voltage swing EDP configuration parameter * @brief 5.preamphasis - preamphasis EDP configuration parameter */ typedef struct { unsigned int enhanced_mode_en; unsigned int lane_rate; unsigned int lane_count; unsigned int voltage_swing; unsigned int preamphasis; } EDPConfig; typedef struct { unsigned int GUID1; unsigned int GUID2; unsigned int GUID3; unsigned int GUID4; unsigned long long GUID; } UInt128; //DP Register access APIs unsigned char DP_RegAccessWrite(unsigned int base_add, FPGARegsDefs a_enRegsDefs , unsigned int a_nPropValue); unsigned char DP_RegAccessRead(unsigned int base_add, FPGARegsDefs a_enRegsDefs , unsigned int *a_nPropValue); //Driver APIs //RX unsigned char DP_RX_EDID_Bulk_Config (unsigned int EDID_reg_val); unsigned char DP_RX_EDID_Single_Config (unsigned int EDID_add , unsigned int EDID_reg_val); unsigned char DP_RX_Video_Stream_MSA_Info (unsigned int stream_number); unsigned char DP_RX_Link_Sink_Status (void); unsigned char DP_RX_Get_Training_Status (void); unsigned char DP_RX_Main_Video_Info_Stream (unsigned int stream_number); unsigned char DP_RX_Audio_Time_Stamp (void); unsigned char DP_RX_Audio_Info(void); //TX unsigned char DP_TX_CD_Capabilities (void); unsigned char DP_TX_EDID_Capabilities (void); unsigned char DP_TX_Training_Status (void); unsigned char DP_TX_Configure_MSA (unsigned int resolution , unsigned int bpc , unsigned int ppc ,unsigned int pixel_format ); unsigned char DP_TX_Enable_Audio(const AudioConfig *audioConfig); unsigned char DP_TX_Enable_Disable_Main_Stream(unsigned int En); unsigned char DP_TX_Resolution_Lock(void); unsigned char DP_TX_EDP_Fast_Link(const EDPConfig *edpConfig); unsigned char DP_TX_Configure_MSA_Stream (unsigned int stream_number , unsigned int resolution , unsigned int pixel_format); //MST related APIs //TX unsigned char DP_TX_Link_Address(unsigned int port_number , unsigned int vc_payload_id , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *number_of_port, UInt128 *result ); unsigned char DP_TX_Allocate_Payload(unsigned int port_number , unsigned int vc_payload_id ,unsigned int bpc, unsigned int pixel_clock_frequency, unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *alloc_reply ); unsigned char DP_TX_Enum_Path_Resources(unsigned int port_number , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *enum_path_reply ); unsigned char DP_TX_Connection_Status_Notify(void); unsigned char DP_TX_PBN_Calculation(unsigned int bpc , unsigned int pixel_clock_frequency , unsigned int *pbn); unsigned char DP_TX_Clear_Payload_Table(unsigned int port_number , unsigned int RAD1 , unsigned int RAD2 ,unsigned int link_count , unsigned int *clear_payload_id_reply );