Implements Debayer block.
LFCPNX-100, LFD2NX1-40, LFD2NX-17, LIFCL-17, LIFCL-33, LIFCL-40, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70
| 1.2.2 |
Fixed combinational loop issue found in last release. |
| 1.2.1 |
Removed license strings. Fixed an issue in proper handling of PPC during vertical blanking period. Fixed an issue in bus width computaton of AXI4-Stream Receiver data. Fixed an issue in TVALID behavior during vertical blanking. Fixed testbench related issues. |
| 1.2.0 |
Fixed issues in bus interface connectivity. Fixed issues in handling TVALID going LOW during vertical blanking period. Other minor IP enhancements. |
| 1.1.0 |
Added support for Avant device. Timing improvements and resource utilization optimizations. Added support for partial resolution. Added regresssion support in Verilog testbench. |
| 1.0.0 | Initial release. |