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IT IS THE USER' S RESPONSIBILITY TO VERIFY THE USER SOFTWARE DESIGN FOR CONSISTENCY AND FUNCTIONALITY THROUGH THE USE OF FORMAL SOFTWARE VALIDATION METHODS. ------------------------------------------------------------------ ================================================================== */ #ifndef _DDR_MC_AVANT_H_ #define _DDR_MC_AVANT_H_ /* Driver version */ #define LPDDR4_DRV_VER "v24.01.00" /** * @brief : Control Register name, address and offset */ #define FEATURE_CTRL_REG (0x200U) #define RESET_REG (0x204U) #define SETTINGS_REG (0x208U) #define PHY_CLOCK_REG (0x20CU) #define INT_STATUS_REG (0x210U) #define INT_ENABLE_REG (0x214U) #define INT_SET_REG (0x218U) /* Debug purpose only */ #define INIT_CTRL_REG (0x201C) /* Reserved for use by internal CPU */ #define TRN_OP_REG (0x220U) #define STATUS_REG (0x224U) #define TIMEOUT_REG (0x228U) #define TIMER_RELOAD_REG (0x22CU) #define MRW_CTRL_REG (0x230U) #define SCRATCH_0_REG (0x240U) /* Debug purpose only */ #define SCRATCH_1_REG (0x244U) /* Debug purpose only */ #define TRIM_SETTINGS_1 (0x250U) #define ODT_SETTING (0x254U) #define SUCCESS 1 #define FAILURE 0 #define IS_NULL 0U #define OUT_OF_RESET (0x01U) #define TRN_EN (0x1FU) #define TRN_BIT_LVL_SWEEP_EN (0x1DFU) #define TRN_BIT_LVL_SWEEP_DIS (0xDFU) #define LPDDR_DONE_BITS (0x0000007F) #define LPDDR_ERR_DONE_BITS (0x00005F7F) #define PLL_LOCK_BIT (0x02U) #define DDR_FREQ (1066) typedef struct{ unsigned int lpddr4_base_address; }lpddr4; /** * @brief : Feature Control Register (FEATURE_CTRL_REG) */ typedef union{ struct{ unsigned int ecc_en : 1; unsigned int dbi_en : 1; unsigned int fea_rsvd_1 : 1; unsigned int gear_ratio : 1; unsigned int fea_rsvd_2 : 4; unsigned int ddr_type : 4; unsigned int ddr_width : 4; unsigned int num_ranks : 1; unsigned int fea_rsvd_3 : 3; unsigned int reset_init_by_phy : 1; unsigned int fea_rsvd_4 : 11; }fields; unsigned int reg; }feature_ctrl_reg_t; /** * @brief : Reset Register (RESET_REG) */ typedef union{ struct{ unsigned int cpu_reset_n : 1; unsigned int phy_reset : 1; unsigned int res_rsvd : 30; }fields; unsigned int reg; }reset_reg_t; /** * @brief : Settings Register (SETTINGS_REG) */ typedef union{ struct { unsigned int write_latency : 8; unsigned int read_latency : 8; unsigned int cmd_freq : 12; unsigned int set_rsvd : 4; }fields; unsigned int reg; }settings_reg_t; /** * @brief : PHY Clock Register (PHY_CLOCK_REG) */ typedef union{ struct { unsigned int disable_clkophy : 1; unsigned int pll_lock : 1; unsigned int pll_reset : 1; unsigned int prim_rst_en_cfc : 1; unsigned int pll_refclk : 12; unsigned int phy_clk_rsvd : 16; }fields; unsigned int reg; }phy_clk_reg_t; /** * @brief : Interrupt Status Register (INT_STATUS_REG) */ typedef union{ struct { unsigned int trn_done_int : 1; unsigned int trn_err_int : 1; unsigned int int_sts_rsvd : 30; }fields; unsigned int reg; }int_status_reg_t; /** * @brief : Interrupt Enable Register (INT_ENABLE_REG) */ typedef union{ struct { unsigned int trn_done_en : 1; unsigned int trn_err_en : 1; unsigned int int_en_rsvd : 30; }fields; unsigned int reg; }int_enable_reg_t; /** * @brief : Training Operation Register (TRN_OP_REG) */ typedef union{ struct { unsigned int init_en : 1; unsigned int cbt_en : 1; unsigned int write_lvl_en : 1; unsigned int read_trn_en : 1; unsigned int write_trn_en : 1; unsigned int ca_vref_training_en : 1; unsigned int mc_vref_training_en : 1; unsigned int mem_vref_training_en : 1; unsigned int bit_lvl_trim_sweep_en : 1; unsigned int trn_op_rsvd : 23; }fields; unsigned int reg; }trn_op_reg_t; /** * @brief : Training Status Register (TRN_STATUS_REG) */ typedef union{ struct { unsigned int init_done : 1; unsigned int cbt_done : 1; unsigned int write_lvl_done : 1; unsigned int read_trn_done : 1; unsigned int write_trn_done : 1; unsigned int scl_done : 1; unsigned int rank_0_done : 1; unsigned int rank_1_done : 1; unsigned int cbt_err : 1; unsigned int write_lvl_err : 1; unsigned int read_trn_err : 1; unsigned int write_trn_err : 1; unsigned int scl_err : 1; unsigned int trn_sts_rsvd1 : 1; unsigned int err_on_rank : 2; unsigned int bit_lvl_trim_sweep_done : 1; unsigned int trn_sts_rsvd2 : 3; unsigned int retaining_count : 1; unsigned int trn_sts_rsvd3 : 8; }fields; unsigned int reg; }trn_status_reg_t; /** * @brief : Trim Settings 1 Register (TRIM_SETTINGS_1_REG) */ typedef union{ struct { unsigned int ck_dly_val : 8; unsigned int ck_dly_val_incr : 1; unsigned int trim_rsvd1 : 7; unsigned int adrctrl_dly_val : 8; unsigned int adrctrl_dly_val_inc : 1; unsigned int trim_rsvd2 : 7; }fields; unsigned int reg; }trim_settings_1_reg; /** * @brief : ODT Settings Register (ODT_SETTINGS_REG) */ typedef union{ struct { unsigned int ca_odt_val : 3; unsigned int odt_rsvd1 : 1; unsigned int dq_odt_val : 3; unsigned int soc_odt_val : 3; unsigned int odte_ck : 1; unsigned int odte_cs : 1; unsigned int odte_ca : 1; unsigned int X8ODTD : 2; unsigned int odt_rsvd2 : 16; }fields; unsigned int reg; }odt_settings_reg; /** * @brief : Enum LPDDR Training Error codes */ typedef enum { NO_FAIL = 0, CBT_FAIL, WR_LVL_FAIL, RD_TRN_FAIL, WR_TRN_FAIL, OTHER_FAIL }LPDDR_RET; /* APIs */ LPDDR_RET lpddr4_init(lpddr4 *instance_ptr, unsigned int base_addr); unsigned int lpddr4_GetFeatureControlReg(lpddr4 *InstancePtr, unsigned int *reg_data); unsigned int lpddr4_GetSettingReg(lpddr4 *InstancePtr, unsigned int *reg_data); unsigned int lpddr4_GetPhyClockReg(lpddr4 *InstancePtr, unsigned int *reg_data); unsigned int lpddr4_TrainingErrorInterruptEnable(lpddr4 *InstancePtr); unsigned int lpddr4_TrainingErrorInterruptDisable(lpddr4 *InstancePtr); unsigned int lpddr4_TrainingDoneInterruptEnable(lpddr4 *InstancePtr); unsigned int lpddr4_TrainingDoneInterruptDisable(lpddr4 *InstancePtr); unsigned int lpddr4_GetTrainingOperationReg(lpddr4 *instancePtr, unsigned int *reg_data); unsigned int lpddr4_GetStatusReg(lpddr4 *instancePtr, unsigned int *reg_data); #endif