DDR_Memory_Controller

Description

The Lattice Semiconductor DDR Memory Controller IP Core provides a turnkey solution consisting of a controller, DDRPHY, and associated clocking and training logic to interface with DDR4 and LPDDR4 SDRAM. The IP Core is implemented in System Verilog HDL using the Lattice Radiant software integrated with the Synplify Pro synthesis tool. The Memory Controller simplifies the interfacing with external DDR4 and LPDDR4 memory for user applications.

Devices Supported

LAV-AT-E30, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70, LN2-CT-20

References

Release Notes

2.4.0 IP Release Notes
2.3.0 Change IP name from Memory Controller for Avant Devices to DDR Memory Controller.
 Added support for LKH-CT-20 and LKH-MH-20 devices.
 Updated write and read latency options.
 Updated PLL to v2.6.0.
 Disabled the Enable Power Down option because of the issue found on HW.
2.2.0 Added driver support for LPDDR4.
 Supported APB disable in the Example Design.
2.1.0 Added support for LAV-AT-E30 device.
 Added LPDDR4 read DBI Support.
 Added Dual Rank Support.
 Improve DDR4 Bus efficiency.
 Validated DDR4 666, 800, 933, 1066, and 1200MHz on the board.
 Validated LPDDR4 1200MHz on the board.
2.0.0 Added DDR4 support.
 DDR4 is not yet HW Validated.
1.3.0 Added support for LAV-AT-G70 and LAV-AT-X70 devices.
 Validated 350, 400, 533, 666, 800, 933, and 1066MHz on the board.
 Added powerdown support.
1.2.0 Enhance AXI4 I/F to support:
  • Burst length from 1 to 64 beats
  • Any combination of burst length and burst size
  • Unaligned transfer using WSTRB
  • AXI4 data width less than DDR data width * 8
    • Validated 266, 300, 350, 400, 533, 666 and 800MHz on the board.
     Added PHY-side and DRAM-side DQ_VREF training support.
     Disabled powerdown support for this version.
    1.1.0 Added support for DDR clock frequency != 800MHz.
     Enabled Post-Synthesis and Post-PAR simulations.
     Validated at 533MHz DDR clock, will validate other frequencies in next release.
    1.0.0 Initial release.