The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller
is a general-purpose memory controller that interfaces with industry standard DDR3
memory devices and modules compliant with the JESD-79.3 specification.
LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100
| 1.4.0 |
Updated read training logic based on validation in the board. Added option to disable the internal PLL. Updated the selectable values for Select Memory and RefClock attributes. Changed the default value of Controller Reset to Memory attributes. Updated the testbench to add write delay that would match with the PHY delay settings that worked on the board. Fixed the cmd_burst_cnt_i=2 issue when 8:1 gearing ratio. |
| 1.3.0 | Updated for Radiant 3.0. |
| 1.2.1 | Updated PLL instance. |
| 1.2.0 | Added LFCPNX support. |
| 1.1.1 | Improved performance for 8:1 gearing ratio. |
| 1.1.0 |
Updated for Radiant 2.1. Added 8:1 gearing ratio support. Added eval folder. Added Certus-NX support. Updated clock signal names: clk_i, sclk_o. Updated PLL instance. |
| 1.0.1 | Updated for Radiant 2.0 Service Pack 1. |
| 1.0.0 | Preliminary release. |