The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller
is a general-purpose memory controller that interfaces with industry standard DDR3
memory devices and modules compliant with the JESD-79.3 specification.
LIFCL
| 1.0.0 | Preliminary release. |
Post-Route Gate-Level simulation hangs when Global Set and Reset (GSR) inference is enabled for Synplify Pro (Enabled by default).
Workaround: Disable GSR inference by double clicking on active Strategy and setting Synplify Pro -> Force GSR to False (default is Auto)
Bug number: DNG-8676