The Lattice Semiconductor DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core is an Open Computer Project (OCP) Data Center – Secure Control Module (DC-SCM) Standards compatible solution which is introduced in the DC-SCM 2.0 Specification. LTPI is a protocol and interface designed for tunneling various low-speed signals between Host Processor Module (HPM) and Secure Control Module (SCM). The LTPI protocol goes over the LVDS (Low Voltage Differential Signals) electrical interfaces supported by majority of the CPLDs and FPGAs. This is the next generation protocol for DC-SCM 2.0 that serves as a replacement for two Serial GPIO (SGPIO) interfaces. The LVDS interface provides higher bandwidth and better scalability than the SGPIO interface. It allows for tunneling of not only GPIOs but also low speed serial interfaces such as I2C and UART. It is also extensible with additional proprietary OEM interfaces and provides support for raw Data tunneling between HPM and SCM CPLDs. It also provides a solution for minimal wire connection between two FPGAs.
MachXO3L, MachXO3LF, MachXO3D, Mach-NX, MachXO5-NX
| 1.6.0 | Release Notes |
| 1.5.1 |
Mask unused APB CSR address (31:7) bits for Propel compatibility. |
| 1.5.0 |
Added MCTP over I2C channel support. Updated CRC implementation. - When LTPI version selected is 1.1 or later, CRC is computed without inverted/reflected input and output. - For older version, CRC is computed with inverted/reflected input and output. Fixed minor issue in packet parser module. Other minor GUI enhancements. |
| 1.4.4 |
Added an optional configurable built-in timer for I2C channel. Added an optional STOP event generation feature for I2C CSR reset when built-in timer is disabled. Updated NL GPIO tunneling implementation. - Number of virtual input and output ports is always the same. - Frame counter starts at count 0 instead of 1. Added I2C related flags in interrupt register. Added new debug ports. Other minor GUI enhancements. |
| 1.4.3 |
Enhanced IP implementation to resolve issues found in MachXO5-NX HW validation. |
| 1.4.2 |
Added support for I2C topology with external I2C target devices in the I2C controller side. - Previous version of the IP requires that no other external I2C target device can exist in the I2C controller side. Fixed an issue in aligner logic. Fixed an issue in clock compensation logic of SDR mode for MachXO5-NX device. Changed default value of "Enable Clock Compensation" attribute to "Enabled". Updated sync_rdy_o output port to be always available in the generated IP. Other minor IP enhancements. |
| 1.4.1 |
Fixed an issue with Data Channel read operation. Fixed a corner case issue related to I2C start and stop operation. Fixed LTPI version to 1.0 in GUI. |
| 1.4.0 |
Enhanced Data Channel support for better usability. - Separated APB interface for IP CSR and Data Channel access for SCM mode. Minor enhancement in system bus support. |
| 1.3.0 |
Added support for MachXO5-NX device. Expanded UART bus support from 8 to 24 maximum. Enhanced Default and Custom I/O frame: - For Default I/O Frame, channels can now be disabled. - For Custom I/O Frame, sequence of channels in the frame is now customizable. Added new tab in GUI for Frame Format view. Added descriptions for each attribute in GUI when hovered. Added new debug ports. Other minor IP enhancements. |
| 1.2.1 |
Fixed an issue in I2C repeated start operations. |
| 1.2.0 |
Added support for Mach-NX device. Fixed minor bug in interrupt reporting. |
| 1.1.1 |
Enhanced word alignment algorithm. |
| 1.1.0 |
Initial release for OCP DC-SCM 2.0 LTPI ver 1.0 compliance. |
| 1.0.0 |
Initial release. |